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State Machine 的代码
statmach_altera.vhd
-- MAX+plus II VHDL Example
-- State Machine
-- Copyright (c) 1994 Altera Corporation
-- download from: www.pld.com.cn & www.fpga.com.cn
Library IEEE ;
use IEEE.std_logic_1164.all ;
ENTIT
state_moor_mealy.txt
-- State Machine with Moore and Mealy outputs
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity mealy1 is port(
clk, rst: in
state_variable.txt
-- State Machine using Variable
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
ENTITY fsm2 IS
PORT(clock,x : IN BIT; z : OUT BIT);
END fsm
moor1.txt
-- Moore State Machine with explicit state encoding
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity moore2 is port(
clk, rst:
moor2.txt
-- Moore State Machine with Concurrent Output Logic
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity moore1 is port(
clk, rst:
up3_clock.smp_dump.txt
State Machine - |UP3_CLOCK|W_current_state
Name W_current_state.w_delay W_current_state.w_stop W_current_state.w_check_ack9 W_current_state.w_check_ack8 W_current_state.w_check_ack7 W_current_state
dstate2a.abl
module dstate2a
title 'State machine showing how an arbitrary default state can be used
to recover from illegal states. Dave Pellerin - Data I/O Corp.'
dstate device 'p16r4';
cl
sequence.abl
module Sequence
title 'State machine example D. B. Pellerin Data I/O Corp';
sequence device 'p16r4';
q1,q0 pin 14,15 istype 'reg,invert';
dstate2b.abl
module dstate2b
title 'State machine showing how an arbitrary default state can be used
to recover from illegal states. Dave Pellerin - Data I/O Corp.'
dstate device 'p16r4';
cl
statmach.vhd
-- MAX+plus II VHDL Example
-- State Machine
-- Copyright (c) 1994 Altera Corporation
ENTITY statmach IS
PORT(
clk : IN BIT;
input : IN BIT;
reset : IN BIT;
output : OUT BIT);
END