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State Machine 的代码
up3_clock.smp_dump.txt
State Machine - |UP3_CLOCK|next_command
Name next_command.display_clear next_command.display_off next_command.reset3 next_command.hold next_command.reset1 next_command.toggle_e next_command.return_
traffic_ls.v
//
// Copyright (c) 2000 Exemplar Logic Inc. All rights reserved.
//
//
// This is a typical example of a state machine description
// in Verilog HDL.
// Two always statements, one to update the st
statmach_altera.v
// State Machine
// download from: www.pld.com.cn & www.fpga.com.cn
module statmach(clk, in, reset, out);
input clk, in, reset;
output out;
reg out;
reg state;
parameter s
bcdcounter4.vhd
--
-- BCDCOUNTER4.VHD
--
-- This is 4 digic BCD up counter.
-- The state machine contains 2 states as follows:
--
-- gate = 1
-- _______________
--
dhcpcstate1.c
/* dhcpcState1.c - DHCP client runtime state machine (lease acquisition) */
/* Copyright 1984 - 2002 Wind River Systems, Inc. */
#include "copyright_wrs.h"
/*
modification history
------------------
dhcpcstate2.c
/* dhcpcState2.c - DHCP client runtime state machine (lease maintenance) */
/* Copyright 1984 - 2002 Wind River Systems, Inc. */
#include "copyright_wrs.h"
/*
modification history
------------------
dhcpcboot.c
/* dhcpcBoot.c - DHCP client finite state machine definition (boot time) */
/* Copyright 1984 - 2002 Wind River Systems, Inc. */
#include "copyright_wrs.h"
/*
modification history
------------------
dstate2a.abl
module dstate2a
title 'State machine showing how an arbitrary default state can be used
to recover from illegal states. Dave Pellerin - Data I/O Corp.'
dstate device 'p16r4';
cl
sequence.abl
module Sequence
title 'State machine example D. B. Pellerin Data I/O Corp';
sequence device 'p16r4';
q1,q0 pin 14,15 istype 'reg,invert';
dstate2b.abl
module dstate2b
title 'State machine showing how an arbitrary default state can be used
to recover from illegal states. Dave Pellerin - Data I/O Corp.'
dstate device 'p16r4';
cl