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State Machine 的代码
03.02.00_example_3-2.v
/**********************************************************************
* Verilog style state machine model using `define and parameters
*
* Author: Stuart Sutherland
*
* (c) Copyright 2003, Suth
gd18-01.cpp
// ============================================================================
// GD18-01.cpp
// Simple Finite State Machine Demo
// =============================================================
traffic_ls.v
//
// Copyright (c) 2000 Exemplar Logic Inc. All rights reserved.
//
//
// This is a typical example of a state machine description
// in Verilog HDL.
// Two always statements, one to update the st
statmach_altera.v
// State Machine
// download from: www.pld.com.cn & www.fpga.com.cn
module statmach(clk, in, reset, out);
input clk, in, reset;
output out;
reg out;
reg state;
parameter s
play_logic_state_machine.vhd
-- **************************************************************
-- File: play_logic_state_machine.vhd
--
-- Purpose: This file implements the Play Logic state machine
-- which performs the
power_ctrl.vhd
-- **************************************************************
-- File: power_ctrl.vhd
--
-- Purpose: This file implements the Power Control Logic state
-- machine which controls the rese
main_ctrl_state_machine.vhd
-- **************************************************************
-- File: main_ctrl_state_machine.vhd
--
-- Purpose: This file implements the MP3 Main Control State
-- machine. Based on ei
ft_water
#include
#include
#define uchar unsigned char
//#define PSM_Version_UG // PSM state machine from the User's Guide is used.
#define PSM_Version_Advanced // advanc
gd18-01.cpp
// ============================================================================
// GD18-01.cpp
// Simple Finite State Machine Demo
// =============================================================
使用变量的状态机.txt
-- State Machine using Variable
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
ENTITY fsm2 IS
PORT(clock,x : IN BIT; z : OUT BIT);
END fsm