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找到约 102,371 项符合 State Machine 的代码

state_areset.txt

-- State Machine with Asynchronous Reset -- dowload from: www.fpga.com.cn & www.pld.com.cn library ieee; use ieee.std_logic_1164.all; entity stmch1 is port(clk, in1, rst: in std_logic;

mealy1.txt

-- Mealy State Machine with Registered Outputs -- dowload from: www.fpga.com.cn & www.pld.com.cn library ieee; use ieee.std_logic_1164.all; entity mealy1 is port( clk, rst: in

statmach_altera.vhd

-- MAX+plus II VHDL Example -- State Machine -- Copyright (c) 1994 Altera Corporation -- download from: www.pld.com.cn & www.fpga.com.cn Library IEEE ; use IEEE.std_logic_1164.all ; ENTIT

state_moor_mealy.txt

-- State Machine with Moore and Mealy outputs -- dowload from: www.fpga.com.cn & www.pld.com.cn library ieee; use ieee.std_logic_1164.all; entity mealy1 is port( clk, rst: in

state_variable.txt

-- State Machine using Variable -- dowload from: www.fpga.com.cn & www.pld.com.cn library ieee; use ieee.std_logic_1164.all; ENTITY fsm2 IS PORT(clock,x : IN BIT; z : OUT BIT); END fsm

moor1.txt

-- Moore State Machine with explicit state encoding -- dowload from: www.fpga.com.cn & www.pld.com.cn library ieee; use ieee.std_logic_1164.all; entity moore2 is port( clk, rst:

moor2.txt

-- Moore State Machine with Concurrent Output Logic -- dowload from: www.fpga.com.cn & www.pld.com.cn library ieee; use ieee.std_logic_1164.all; entity moore1 is port( clk, rst:

07.01.02_example_7-3.sv

/********************************************************************** * Finite State Machine modeled with reversed case and enumerated types * * Author: Stuart Sutherland * * (c) Copyright 2003

07.01.05_example_7-4.sv

/********************************************************************** * Finite State Machine modeled with bad assignment to enumerated variable * * Author: Stuart Sutherland * * (c) Copyright 2

03.02.00_example_3-3.sv

/********************************************************************** * SystemVerilog style state machine model using enumerated types * * Author: Stuart Sutherland * * (c) Copyright 2003, Suth