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State Machine 的代码
莫尔型状态机2.txt
-- Moore State Machine with Concurrent Output Logic
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity moore1 is port(
clk, rst:
莫尔型状态机1.txt
-- Moore State Machine with explicit state encoding
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity moore2 is port(
clk, rst:
用状态机设计的交通灯控制器.v
//
// Copyright (c) 2000 Exemplar Logic Inc. All rights reserved.
//
//
// This is a typical example of a state machine description
// in Verilog HDL.
// Two always statements, one to update the st
一个简单的状态机.v
// State Machine
// download from: www.pld.com.cn & www.fpga.com.cn
module statmach(clk, in, reset, out);
input clk, in, reset;
output out;
reg out;
reg state;
parameter s
prog18.asm
; PROG18 - State Machines
;
; This Application Demonstrates how a set of traffic lights could
; be controlled in the 8051 using a State Machine and Table Jumps.
;
; This program will run i
statemachine.java
//: statemachine2:StateMachine.java
// A table-driven state machine
package statemachine2;
import java.util.*;
public class StateMachine {
private State state;
private Map map = new HashMa
condition.java
//: statemachine2:Condition.java
// Condition function object for state machine
package statemachine2;
public interface Condition {
boolean condition(Input i);
} ///:~
transition.java
//: statemachine2:Transition.java
// Transition function object for state machine
package statemachine2;
public interface Transition {
void transition(Input i);
} ///:~
mousetraptest.java
//: statemachine:mousetrap1:MouseTrapTest.java
// State Machine pattern using 'if' statements
// to determine the next state.
package statemachine.mousetrap1;
import statemachine.mouse.*;
import
vending.v
/*
* FINITE STATE MACHINE
*
* This file is automatically generated on Sse Command "State Machine/Save"
* DO NOT MODIFY this file - it will get overwritten.
*
* The graphic visualization f