代码搜索：State Machine
找到约 10,000 项符合「State Machine」的源代码
代码结果 10,000
www.eeworm.com/read/260961/4326823
vif state1.vif
#
# Synplicity Verification Interface File
# Generated using Synplify-pro
#
# Copyright (c) 1996-2005 Synplicity, Inc.
# All rights reserved
#
# Set logfile options
vif_set_result_file stat
www.eeworm.com/read/260961/4326825
srm state1.srm
f "noname"; #file 0
f "noname"; #file 1
f "c:\eda\synplicity\fpga_81\lib\lucent\ec.v"; #file 2
f "c:\prj\fsm_abc\state1\state1.v"; #file 3
VNAME 'LUCENT.OB.PRIM'; # view id 0
VNAME 'LUCENT.IB.PRI
www.eeworm.com/read/260961/4326826
vqm state1.vqm
//
// Written by Synplify
// Synplify 8.1.0, Build 539R.
// Fri Dec 16 14:48:22 2005
//
// Source file index table:
// Object locations will have the form :
// file 0 "noname"
// f
www.eeworm.com/read/260961/4326827
tlg state1.tlg
Selecting top level module state1
@N:"C:\prj\FSM_abc\state1\state1.v":6:7:6:12|Synthesizing module state1
@N: CL201 :"C:\prj\FSM_abc\state1\state1.v":27:0:27:5|Trying to extract state machine for
www.eeworm.com/read/260961/4326828
srs state1.srs
#
#
#
# Created by Synplify Verilog HDL Compiler version 3.1.0, Build 049R from Synplicity, Inc.
# Copyright 1994-2004 Synplicity, Inc. , All rights reserved.
# Synthesis Netlist written on Fri D
www.eeworm.com/read/260961/4326829
plg state3.plg
@P: Worst Slack : -0.484
@P: state2|clk - Estimated Frequency : 309.6 MHz
@P: state2|clk - Requested Frequency : 364.2 MHz
@P: state2|clk - Estimated Period : 3.230
@P: state2|clk - Requested
www.eeworm.com/read/260961/4326830
prf state3.prf
#
# Logical Preferences generated for Lucent by Synplify 8.1.0, Build 532R.
#
# Period Constraints
FREQUENCY PORT "clk" 364.2 MHz;
# Output Constraints
# Input Constraints
BLOCK ASYNCPATHS;
www.eeworm.com/read/260961/4326832
tlg state3.tlg
Selecting top level module state2
@N:"C:\prj\FSM_abc\state3\state3.v":7:7:7:12|Synthesizing module state2
@N: CL201 :"C:\prj\FSM_abc\state3\state3.v":28:0:28:5|Trying to extract state machine for
www.eeworm.com/read/260961/4326833
edn state3.edn
(edif state2
(edifVersion 2 0 0)
(edifLevel 0)
(keywordMap (keywordLevel 0))
(status
(written
(timeStamp 2005 12 16 15 26 4)
(author "Synplicity, Inc.")
(program
www.eeworm.com/read/260961/4326834
srs state3.srs
#
#
#
# Created by Synplify Verilog HDL Compiler version 3.1.0, Build 049R from Synplicity, Inc.
# Copyright 1994-2004 Synplicity, Inc. , All rights reserved.
# Synthesis Netlist written on Fri D