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State Machine 的代码
eapol_sm.c
/*
* WPA Supplicant / EAPOL state machines
* Copyright (c) 2004-2005, Jouni Malinen
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the
eap.c
/*
* WPA Supplicant / EAP state machines (RFC 4137)
* Copyright (c) 2004-2005, Jouni Malinen
*
* This program is free software; you can redistribute it and/or modify
* it under the term
fsm_demo.c
/* +++Date last modified: 05-Jul-1997 */
/*
** code snippet demonstrating a finite state machine (FSM)
*/
typedef enum {s0,s1,s2,s3,s4,...,sn,sexit} state;
state nextstate;
int done = 0;
fsm.c
/*
** code snippet demonstrating a finite state machine (FSM)
*/
typedef enum {s0,s1,s2,s3,s4,...,sn,sexit} state;
state nextstate;
int done = 0;
nextstate = s0; /* set up to start with
statmach.v
// MAX+plus II Verilog Example
// State Machine
// Copyright (c) 1997 Altera Corporation
module statmach(clk, in, reset, out);
input clk, in, reset;
output out;
reg out;
reg sta
statmach.vhd
-- MAX+plus II VHDL Example
-- State Machine
-- Copyright (c) 1994 Altera Corporation
ENTITY statmach IS
PORT(
clk : IN BIT;
input : IN BIT;
reset : IN BIT;
output : OUT BIT);
END
netfsm.c
/*****************************************************************************
* netfsm.c - Network Control Protocol Finite State Machine program file.
*
* portions Copyright (c) 1997 by Global Ele
statmach.vhd
-- MAX+plus II VHDL Example
-- State Machine
-- Copyright (c) 1994 Altera Corporation
ENTITY statmach IS
PORT(
clk : IN BIT;
input : IN BIT;
reset : IN BIT;
output : OUT BIT);
END
pppfsm.c
/*
* PPPFSM.C -- PPP Finite State Machine
*
* This implementation of PPP is declared to be in the public domain.
*
* Acknowledgements and correction history may be found in PPP.C
*/
#i
使用变量的状态机.txt
-- State Machine using Variable
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
ENTITY fsm2 IS
PORT(clock,x : IN BIT; z : OUT BIT);
END fsm