代码搜索：State Machine

找到约 10,000 项符合「State Machine」的源代码

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热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
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prd state3.prd

#-- Synplicity, Inc. #-- Version Synplify Pro 8.1 #-- Project file C:\prj\FSM_abc\state3\state3.prd #-- Written on Fri Dec 16 16:54:36 2005 # ### Watch Implementation type ### # watch_impl -a
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msg state3.msg

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plg state3.plg

@P: Worst Slack : -0.484 @P: state2|clk - Estimated Frequency : 309.6 MHz @P: state2|clk - Requested Frequency : 364.2 MHz @P: state2|clk - Estimated Period : 3.230 @P: state2|clk - Requested
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prf state3.prf

# # Logical Preferences generated for Lucent by Synplify 8.1.0, Build 532R. # # Period Constraints FREQUENCY PORT "clk" 364.2 MHz; # Output Constraints # Input Constraints BLOCK ASYNCPATHS;
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tlg state3.tlg

Selecting top level module state2 @N:"C:\prj\FSM_abc\state3\state3.v":7:7:7:12|Synthesizing module state2 @N: CL201 :"C:\prj\FSM_abc\state3\state3.v":28:0:28:5|Trying to extract state machine for
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edn state3.edn

(edif state2 (edifVersion 2 0 0) (edifLevel 0) (keywordMap (keywordLevel 0)) (status (written (timeStamp 2005 12 16 15 26 4) (author "Synplicity, Inc.") (program
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srs state3.srs

# # # # Created by Synplify Verilog HDL Compiler version 3.1.0, Build 049R from Synplicity, Inc. # Copyright 1994-2004 Synplicity, Inc. , All rights reserved. # Synthesis Netlist written on Fri D
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fse state3.fse

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srm state3.srm

f "noname"; #file 0 f "noname"; #file 1 f "c:\eda\synplicity\fpga_81\lib\lucent\ec.v"; #file 2 f "c:\prj\fsm_abc\state3\state3.v"; #file 3 VNAME 'LUCENT.OB.PRIM'; # view id 0 VNAME 'LUCENT.IB.PRI
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srr state3.srr

#Program: Synplify Pro 8.1 #OS: Windows_NT $ Start of Compile #Fri Dec 16 15:26:02 2005 Synplicity Verilog Compiler, version 3.1.0, Build 049R, built May 3 2005 Copyright (C) 1994-2005, Synp
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