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找到约 102,371 项符合 State Machine 的代码

莫尔型状态机2.txt

-- Moore State Machine with Concurrent Output Logic -- dowload from: www.fpga.com.cn & www.pld.com.cn library ieee; use ieee.std_logic_1164.all; entity moore1 is port( clk, rst:

带莫尔1米勒输出的状态机.txt

-- State Machine with Moore and Mealy outputs -- dowload from: www.fpga.com.cn & www.pld.com.cn library ieee; use ieee.std_logic_1164.all; entity mealy1 is port( clk, rst: in

用状态机实现的计数器.vhd

-- MAX+plus II VHDL Example -- State Machine -- Copyright (c) 1994 Altera Corporation -- download from: www.pld.com.cn & www.fpga.com.cn Library IEEE ; use IEEE.std_logic_1164.all ; ENTIT

莫尔型状态机1.txt

-- Moore State Machine with explicit state encoding -- dowload from: www.fpga.com.cn & www.pld.com.cn library ieee; use ieee.std_logic_1164.all; entity moore2 is port( clk, rst:

ask_mod.smp_dump.txt

State Machine - |ask_mod|fir_ssb:inst3|fir_ssb_new:fir_ssb_new_inst|auk_dspip_avalon_streaming_source:source|source_state Name source_state.end1 source_state.st_err source_state.run1 source_state.s

pie_code.smp_dump.txt

State Machine - |pie_code|fff:inst1|fff_new:fff_new_inst|auk_dspip_avalon_streaming_source:source|source_state Name source_state.end1 source_state.st_err source_state.run1 source_state.sop source_s

uart_top.smp_dump.txt

State Machine - |Uart_top|Txmitt:U4|Tx_State Name Tx_State.stop_halfbit Tx_State.stop_2bit Tx_State.stop_1bit Tx_State.parity Tx_State.shift Tx_State.start Tx_State.start 0 0 0 0 0 0 Tx_State.s

nasm.c

/***************************************************************************** * * Microchip DeviceNet Stack * (Network Access State Machine management source code) * **********************

米勒型状态机.txt

-- Mealy State Machine with Registered Outputs -- dowload from: www.fpga.com.cn & www.pld.com.cn library ieee; use ieee.std_logic_1164.all; entity mealy1 is port( clk, rst: in

mem_ctrl1.smp_dump.txt

State Machine - |mem_ctrl1|sd_if:sd_if1|sd_top:sd_top1|sd_cnfg:u1|state Name state.precharge state.refresh1 state.nop2 state.refresh2 state.load_mode state.idle state.all_done state.idle 0 0 0 0