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State Machine 的代码
带同步复位的状态机.txt
-- State Machine with Asynchronous Reset
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity stmch1 is
port(clk, in1, rst: in std_logic;
莫尔型状态机2.txt
-- Moore State Machine with Concurrent Output Logic
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity moore1 is port(
clk, rst:
莫尔型状态机1.txt
-- Moore State Machine with explicit state encoding
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity moore2 is port(
clk, rst:
lcd_1602.smp_dump.txt
State Machine - |lcd_1602|lcd:inst|state
Name state.SETDDRAM2 state.SETDDRAM1 state.SETCGRAM state.IDLE state.WRITERAM state.SETFUNCTION state.SHIFT state.SWITCHMODE state.SETMODE state.RETURNCURSO
top.smp_dump.txt
State Machine - |top|mouse:mousedata|m1_state
Name m1_state.m1_rising_wait m1_state.m1_rising_edge m1_state.m1_clk_l m1_state.m1_falling_wait m1_state.m1_falling_edge m1_state.m1_clk_h
m1_state.m
statemachine.h
#ifndef STATEMACHINE_H
#define STATEMACHINE_H
//------------------------------------------------------------------------
//
// Name: StateMachine.h
//
// Desc: State machine class. Inher
pppfsm.c
/*
* PPPFSM.C -- PPP Finite State Machine
*
* This implementation of PPP is declared to be in the public domain.
*
* Acknowledgements and correction history may be found in PPP.C
*/
#i
statmach.v
// MAX+plus II Verilog Example
// State Machine
// Copyright (c) 1997 Altera Corporation
module statmach(clk, in, reset, out);
input clk, in, reset;
output out;
reg out;
reg sta
statmach.vhd
-- MAX+plus II VHDL Example
-- State Machine
-- Copyright (c) 1994 Altera Corporation
ENTITY statmach IS
PORT(
clk : IN BIT;
input : IN BIT;
reset : IN BIT;
output : OUT BIT);
END
使用变量的状态机.txt
-- State Machine using Variable
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
ENTITY fsm2 IS
PORT(clock,x : IN BIT; z : OUT BIT);
END fsm