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State Machine 的代码
莫尔型状态机1.txt
-- Moore State Machine with explicit state encoding
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity moore2 is port(
clk, rst:
traffic_ls.v
//
// Copyright (c) 2000 Exemplar Logic Inc. All rights reserved.
//
//
// This is a typical example of a state machine description
// in Verilog HDL.
// Two always statements, one to update the st
statmach_altera.v
// State Machine
// download from: www.pld.com.cn & www.fpga.com.cn
module statmach(clk, in, reset, out);
input clk, in, reset;
output out;
reg out;
reg state;
parameter s
pppfsm.c
/*
* PPPFSM.C -- PPP Finite State Machine
*
* This implementation of PPP is declared to be in the public domain.
*
* Acknowledgements and correction history may be found in PPP.C
*/
#i
使用变量的状态机.txt
-- State Machine using Variable
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
ENTITY fsm2 IS
PORT(clock,x : IN BIT; z : OUT BIT);
END fsm
一个简单的状态机.vhd
-- MAX+plus II VHDL Example
-- State Machine
-- Copyright (c) 1994 Altera Corporation
-- download from: www.pld.com.cn & www.fpga.com.cn
Library IEEE ;
use IEEE.std_logic_1164.all ;
ENTIT
米勒型状态机.txt
-- Mealy State Machine with Registered Outputs
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity mealy1 is port(
clk, rst: in
带同步复位的状态机.txt
-- State Machine with Asynchronous Reset
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity stmch1 is
port(clk, in1, rst: in std_logic;
带莫尔_米勒输出的状态机.txt
-- State Machine with Moore and Mealy outputs
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity mealy1 is port(
clk, rst: in
莫尔型状态机2.txt
-- Moore State Machine with Concurrent Output Logic
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity moore1 is port(
clk, rst: