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State Machine 的代码
state (1).~prjpcb
[Design]
Version=1.0
HierarchyMode=0
ChannelRoomNamingStyle=0
OutputPath=
ChannelDesignatorFormatString=$Component_$RoomName
ChannelRoomLevelSeperator=_
OpenOutputs=1
ArchiveProject=0
Timesta
state.nsx
State
*SPICE Netlist generated by Advanced Sim server on 2009-6-13 15:43:26
*Add Node Bridge Data
ADVB1 [BIT1$DV BIT2$DV BIT3$DV N1$DV N10$DV N11$DV N12$DV N2$DV N3$DV]
+ [BIT1 BIT2 BIT3 N1 N10
state.sim
Circuit: State
Date: 星期六 六月 13 15:43:26 2009
Total elapsed time: 2.172 seconds.
state.cfg
[Analyses Setup]
DCAnalysis=False
ACAnalysis=False
TransientAnalysis=True
TransferFunction=False
NoiseAnalysis=False
OPAnalysis=False
ParamSweep=False
TempSweep=False
MonteCarlo=False
Always
state.prjpcb
[Design]
Version=1.0
HierarchyMode=0
ChannelRoomNamingStyle=0
OutputPath=
ChannelDesignatorFormatString=$Component_$RoomName
ChannelRoomLevelSeperator=_
OpenOutputs=1
ArchiveProject=0
Timesta