代码搜索结果
找到约 10,000 项符合
State Machine 的代码
state.vb
Public Class State
'//this will execute when the state is entered
Public Overridable Sub Enter(ByVal m As Miner)
End Sub
'//this is the state's normal update function
Publ
state.vhd
library ieee;
use ieee.std_logic_1164.all;
entity state is
port(w:in std_logic_vector(16 downto 0);
clk0,rst:in std_logic; ---取序列各位的时钟1Hz
clk1:in std_logic; ---状态转换的时钟1KHz
z:out std_logi
state.bsf
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to
state.pin
-- Copyright (C) 1991-2006 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and a
state.qws
[ProjectWorkspace]
ptn_Child1=Frames
[ProjectWorkspace.Frames]
ptn_Child1=ChildFrames
[ProjectWorkspace.Frames.ChildFrames]
ptn_Child1=Document-0
ptn_Child2=Document-1
ptn_Child3=Document-2
[P
state.done
Sun Oct 26 15:35:54 2008