代码搜索结果

State Machine - |traffic_lights|ctr:u1|stax Name stax.sta4 stax.sta3 stax.sta2 stax.sta1 stax.sta1 0 0 0 0 stax.sta2 0 0 1 1 stax.sta3 0 1 0 1 stax.sta4 1 0 0 1

State Machine - |ctr|stax Name stax.sta4 stax.sta3 stax.sta2 stax.sta1 stax.sta1 0 0 0 0 stax.sta2 0 0 1 1 stax.sta3 0 1 0 1 stax.sta4 1 0 0 1

-- Quartus VHDL Template -- State Machine with Asynchronous Reset (1 block) -- State Machine outputs will be registered LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY vhdl1 IS PORT (

State Machine - |FSM_Moore|sreg Name sreg.a11 sreg.a00 sreg.a1 sreg.a0 sreg.init sreg.init 0 0 0 0 0 sreg.a0 0 0 0 1 1 sreg.a1 0 0 1 0 1 sreg.a00 0 1 0 0 1 sreg.a11 1 0 0 0 1

<mark>State</mark> <mark>Machine</mark> - |main1|<mark>State</mark> Name <mark>State</mark>.<mark>state</mark>_bit_3 <mark>State</mark>.<mark>state</mark>_bit_2 <mark>State</mark>.<mark>state</mark>_bit_1 <mark>State</mark>.<mark>state</mark>_bit_0 <mark>State</mark>.a0 0 0 0 0 <mark>State</mark>.a1 0 1 0 0 <mark>State</mark>.a2 1 0 0 0 <mark>State</mark>.ak0 0 0 0 1 <mark>State</mark>.ak1 1 ...

State Machine - |DE2_LCM_Test|I2S_LCM_Config:u4|mSetup_ST Name mSetup_ST.0000 mSetup_ST.0010 mSetup_ST.0001 mSetup_ST.0000 0 0 0 mSetup_ST.0001 1 0 1 mSetup_ST.0010 1 1 0

State Machine - |seg_check|current_state Name current_state.s6 current_state.s5 current_state.s4 current_state.s3 current_state.s2 current_state.s1 current_state.s0 current_state.s0 0 0 0 0 0 0 0

State Machine - |ADC0809|current_state Name current_state.st6 current_state.st5 current_state.st4 current_state.st3 current_state.st2 current_state.st1 current_state.st0 current_state.st0 0 0 0 0

State Machine - |moore|present_state Name present_state.write present_state.read present_state.decision present_state.idle present_state.idle 0 0 0 0 present_state.decision 0 0 1 1 present_st

/******************************************************************** * Quantum Finite State Machine declarations ("C+" version) * Copyright (c) 2002 Miro Samek, Palo Alto, CA. * All Rights Res