代码搜索结果
找到约 102,371 项符合
State Machine 的代码
usb_out.smp_dump.txt
State Machine - |pc2fpga|STATE
Name STATE.IDLE STATE.READ_2 STATE.READ_1
STATE.IDLE 0 0 0
STATE.READ_2 1 1 0
STATE.READ_1 1 0 1
ad.smp_dump.txt
State Machine - |ad|ad0804:u2|current_state
Name current_state.read2 current_state.read1 current_state.convert current_state.start
current_state.start 0 0 0 0
current_state.convert 0 0 1 1
cu
statmch1.v
//
// Copyright (c) 1995 by Synplicity, Inc.
// You may distribute freely, as long as this header remains attached.
//
// State Machine Example
// Space shuttle controller
// Copyright
statmch2.v
//
// Copyright (c) 1995 by Synplicity, Inc.
// You may distribute freely, as long as this header remains attached.
//
// VCR tape player and recorder state machine
//
// 10 states
`define st
prep3.v
/* PREP3 contains a small state machine
Copyright (c) 1994 Synplicity, Inc.
You may distribute freely, as long as this header remains attached. */
module prep3(CLK, RST, IN, OUT);
input CLK, R
prep4.v
// PREP Benchmark 4, Large State Machine
/* PREP4 contains a large state machine
Copyright (c) 1994 Synplicity, Inc.
You may distribute freely, as long as this header remains attached. */
mo
statmch2.vhd
--
--State machine that tries to guess the next data input value
--
library ieee;
use ieee.std_logic_1164.all;
entity guesser is
port(clk, rst, data : in std_logic;
guess : ou
prep3.vhd
-- PREP Benchmark 3, Small State Machine
-- PREP3 contains a small state machine
-- Copyright (c) 1994-1996 Synplicity, Inc.
-- You may distribute freely, as long as this header remains attached.
prep4.vhd
-- PREP Benchmark 4, Large State Machine
-- PREP4 contains a large state machine
-- Copyright (c) 1994-1996 Synplicity, Inc.
-- You may distribute freely, as long as this header remains attached.
hdl_demo.tlg
Selecting top level module hdl_demo
Synthesizing module alu
Synthesizing module hdl_demo
@N: CL201 :"D:\prj_D\Synplify_Pro\source\verilog\HDL_DEMO.V":38:0:38:5|Trying to extract state machine for r