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Speaker 的代码
yanzou.c
#include
sbit speaker = P2^4;
unsigned char timer0h, timer0l, time;
//--------------------------------------
//单片机晶振采用11.0592MHz
// 频率-半周期数据表 高八位 本软件共保存了四个八度的28个频率数据
code unsigne
usbaudio_abstract.txt
The Audio project is a demo program for the Keil MCB1700
Board using the NXP LPC17xx Microcontroller.
It demonstrates an USB Audio Device - Speaker.
The USB Audio Device is recognized by the ho
usbaudio_abstract.txt
The Audio project is a demo program for the Keil MCB1700
Board using the NXP LPC17xx Microcontroller.
It demonstrates an USB Audio Device - Speaker.
The USB Audio Device is recognized by the ho
cpld
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY Speaker IS
PORT ( clk1 : IN STD_LOGIC;
Tone1 : IN INTEGER RANGE 0 TO 16#7FF#;
SpkS : OUT STD_LOGIC );
END;
A
music_police_siren.v
// music_police_siren.v //警笛鸣声
module music_police_siren(clk, speaker);
input clk;
output speaker;
//
reg [22:0] tone;
always @(posedge clk) tone
music_tune.v
// music_tune.v
module music_tune(clk, speaker);
input clk;
output speaker;
//To play a range of increasing notes, we instantiate a 28 bits counter,
// from which we extract the 6 most signif
_pace.ucf
NET "sysclk" LOC = "p32";
NET "nreset_3828" LOC = "p100";
NET "nreset_cpu" LOC = "p69";
NET "test_led" LOC = "p54";
NET "speaker" LOC = "p56";
NET "cpu_nwait" LOC = "p60";
NET "c
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity song is
port(
clk : in vl_logic;
speaker : out vl_logic;
index : in vl_logic_vect
song.sym
VERSION 5
BEGIN SYMBOL
SYMBOLTYPE BLOCK
TIMESTAMP 2006 5 27 2 2 3
SYMATTR VeriModel "song"
SYMPIN 0 -160 Input clk
SYMPIN 0 -32 Input index(2:0)
SYMPIN 384 -160 Output speaker
SYMPIN 384 -96