代码搜索：Sim

找到约 10,000 项符合「Sim」的源代码

代码结果 10,000
热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
www.eeworm.com/read/208954/4989555

h sim.h

/* ********************************************************************************************************* * uC/GUI * Univers
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www.eeworm.com/read/198135/5089710

run_sim

ncverilog -f ../bin/nc.scr &
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www.eeworm.com/read/198135/5089723

tcl sim.tcl

database -open waves -into ../out/uart -default probe -create -shm uart_test -all -depth all stop -create -time 1000000000ns -relative run quit
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www.eeworm.com/read/192230/5159373

exp sim.exp

# Test Framework Driver for GDB driving a builtin simulator # Copyright 1994, 1997, 1998 Free Software Foundation, Inc. # # This program is free software; you can redistribute it and/or modify # it
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www.eeworm.com/read/190666/5178832

c sim.c

main () { int i; for (i = 1; i < 10000; i++) ; }
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www.eeworm.com/read/188562/5207783

sim_report

############################################################ # # # SIMULATION REPORT # #
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www.eeworm.com/read/188562/5207787

sim_trace

u: Test at 0.0: start processing u: R1 at 0.0: scheduling event type 2 for Output_R1 with delay 0.0 u: R1 at 0.0: waiting for an event u: Input_R2 at 0.0: waiting for an event u: Output_GridInformatio
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www.eeworm.com/read/185715/5236190

h sim.h

/* ********************************************************************************************************* * uC/GUI V3.98 * Univ
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www.eeworm.com/read/183010/5258483

sh sim.sh

#!/bin/bash # # This script runs RTL and gate-level simulation using different simultion tools. # Right now Cadence Verilog-XL and NCSim are supported. # # Author: Damjan Lampret # # # User definiti
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www.eeworm.com/read/182103/5265510

h sim.h

/* *------------------------------------------------------------------- * * SIM -- System Integration Module * * The system integration module (SIM) is used on many Motorola 16- * and 32-bit M
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