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Serial 的代码
serial.prj
verilog work "serial.v"
serial.bld
Release 7.1.04i ngdbuild H.42
Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
Command Line: ngdbuild -intstyle ise -dd d:\test\icx229al/_ngo -nt timestamp -i
-p xc3s400-pq208-4 serial.ngc
serial.lso
work
serial.xst
set -tmpdir __projnav
set -xsthdpdir ./xst
run
-ifn serial.prj
-ifmt mixed
-ofn serial
-ofmt NGC
-p xc3s400-4-pq208
-top serial
-opt_mode Speed
-opt_level 1
-iuc NO
-lso serial.lso
-keep_
serial.v
module serial(clk,rst,reset,sload,sclk); //clk周期为34.92ns
input clk,rst;
output reset,sload,sclk;
reg reset,sload,sclk;
reg [7:0]sa,sb,sc,sd;
reg [3:0]s1,s2,s3,s4,s5;
always@(posedg
serial.syr
Release 7.1.04i - xst H.42
Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
--> Parameter TMPDIR set to __projnav
CPU : 0.00 / 1.64 s | Elapsed : 0.00 / 1.00 s
--> Parameter xsthdpdir set