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Serial 的代码
serial_rd.stx
Release 8.1i - xst I.24
Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
--> Parameter TMPDIR set to ./xst/projnav.tmp
CPU : 0.00 / 0.30 s | Elapsed : 0.00 / 0.00 s
-->
==================
serial_wr.xst
set -tmpdir ./xst/projnav.tmp
elaborate
-ifn serial_wr.prj
-ifmt mixed
serial_rd.xst
set -tmpdir ./xst/projnav.tmp
elaborate
-ifn serial_rd.prj
-ifmt mixed
serial_rw.v
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:15:21 11/13/2007
// Design Name:
// Modul
serial_rd.prj
verilog work "serial_rd.v"
serial_test.bsf
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to
serial_test.vhd
--
-- 本模块的功能是验证实现和PC机进行基本的串口通信的功能。需要在
--PC机上安装一个串口调试工具来验证程序的功能。
-- 程序实现了一个收发一帧10个bit（即无奇偶校验位）的串口控
--制器，10个bit是1位起始位，8个数据位，1个结束
--位。串口的波特律由程序中定义的div_par参数决定，更改该参数可以实
--现相应的波特率。程序当前设定的div_par 的值 ...
serial_pal.v
module serial_pal(clk,reset,en,in,out);
input clk,reset,en,in;
output[3:0] out;
reg[3:0] out;
always @(posedge clk)
begin
if(reset) out
serial2.v
module serial2(q,a,clk);
output q,a;
input clk;
reg q,a;
always @(posedge clk)
begin
a=~q;
q=~q;
end
endmodule
serial1.v
module serial1(q,a,clk);
output q,a;
input clk;
reg q,a;
always @(posedge clk)
begin
q=~q;
a=~q;
end
endmodule