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example_en_16bit_s.vh
/* Verilog Header Created from SCS Schematic example_en_16bit_s.sch
Aug 14, 2003 12:15 */
module example_en_16bit_s( clear_in , clk_in, enable_in, count_out );
input clear_in, clk_in;
out
example_en_16bit_s.vhd
-- VHDL Model Created from SCS Schematic example_en_16bit_s.sch
-- Aug 14, 2003 12:15
-- Automatically generated by vdvhdl version 9.5 Release Build2
library IEEE;
use IEEE.std_logic_1164.a
example_en_4bit.vhd
-- VHDL Model Created from SCS Schematic example_en_4bit.sch
-- Aug 13, 2003 12:31
-- Automatically generated by vdvhdl version 9.5 Release Build2
library IEEE;
use IEEE.std_logic_1164.all;
example_en_4bit.vq
`timescale 1ps / 1ps
/* Verilog Header Created from SCS Schematic example_en_4bit.sch
Aug 13, 2003 12:30 */
module example_en_4bit( clear_in , clk_in, enable_in, count_out );
input clear
example_en_4bit.v
/* Verilog Model Created from SCS Schematic example_en_4bit.sch
Aug 13, 2003 12:30 */
/* Automatically generated by hvveri version 9.5 Release Build2 */
`timescale 1ns/1ns
`define LOGIC
example_en_4bit.vh
/* Verilog Header Created from SCS Schematic example_en_4bit.sch
Aug 13, 2003 12:30 */
module example_en_4bit( clear_in , clk_in, enable_in, count_out );
input clear_in, clk_in;
output [3
example_en_8bit_s.vh
/* Verilog Header Created from SCS Schematic example_en_8bit_s.sch
Aug 14, 2003 11:35 */
module example_en_8bit_s( clear_in , clk_in, enable_in, count_out );
input clear_in, clk_in;
outpu
example_en_8bit_s.v
/* Verilog Model Created from SCS Schematic example_en_8bit_s.sch
Aug 14, 2003 11:35 */
/* Automatically generated by hvveri version 9.5 Release Build2 */
`timescale 1ns/1ns
`define LOGI
example_en_8bit_s.vhd
-- VHDL Model Created from SCS Schematic example_en_8bit_s.sch
-- Aug 14, 2003 11:35
-- Automatically generated by vdvhdl version 9.5 Release Build2
library IEEE;
use IEEE.std_logic_1164.al
example_en_8bit_s.vq
`timescale 1ps / 1ps
/* Verilog Header Created from SCS Schematic example_en_8bit_s.sch
Aug 14, 2003 11:35 */
module example_en_8bit_s( clear_in , clk_in, enable_in, count_out );
input c