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example_24bit_load.v
/* Verilog Model Created from SCS Schematic example_24bit_load.sch
Aug 15, 2003 11:51 */
/* Automatically generated by hvveri version 9.5 Release Build2 */
`timescale 1ns/1ns
`define LOG
example_24bit_load.vhd
-- VHDL Model Created from SCS Schematic example_24bit_load.sch
-- Aug 15, 2003 11:51
-- Automatically generated by vdvhdl version 9.5 Release Build2
library IEEE;
use IEEE.std_logic_1164.a
example_8bit_load.v
/* Verilog Model Created from SCS Schematic example_8bit_load.sch
Aug 15, 2003 10:41 */
/* Automatically generated by hvveri version 9.5 Release Build2 */
`timescale 1ns/1ns
`define LOGI
example_8bit_load.vh
/* Verilog Header Created from SCS Schematic example_8bit_load.sch
Aug 15, 2003 10:40 */
module example_8bit_load( clear_in , clk_in, data, enable_in, load_in, count_out );
input clear_in,
example_8bit_load.vhd
-- VHDL Model Created from SCS Schematic example_8bit_load.sch
-- Aug 15, 2003 10:41
-- Automatically generated by vdvhdl version 9.5 Release Build2
library IEEE;
use IEEE.std_logic_1164.al
example_16bit_load.v
/* Verilog Model Created from SCS Schematic example_16bit_load.sch
Aug 15, 2003 11:19 */
/* Automatically generated by hvveri version 9.5 Release Build2 */
`timescale 1ns/1ns
`define LOG
example_16bit_load.vhd
-- VHDL Model Created from SCS Schematic example_16bit_load.sch
-- Aug 15, 2003 11:19
-- Automatically generated by vdvhdl version 9.5 Release Build2
library IEEE;
use IEEE.std_logic_1164.a
example_16bit_load.vh
/* Verilog Header Created from SCS Schematic example_16bit_load.sch
Aug 15, 2003 11:19 */
module example_16bit_load( clear_in , clk_in, data, enable_in, load_in, count_out );
input clear_in
example_16bit_load.vq
`timescale 1ps / 1ps
/* Verilog Header Created from SCS Schematic example_16bit_load.sch
Aug 15, 2003 11:19 */
module example_16bit_load( clear_in , clk_in, data, enable_in, load_in, coun
example_32bit_load.vh
/* Verilog Header Created from SCS Schematic example_32bit_load.sch
Aug 15, 2003 13:22 */
module example_32bit_load( clear_in , clk_in, data, enable_in, load_in, count_out );
input clear_in