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example_en_4bit.v
/* Verilog Model Created from SCS Schematic example_en_4bit.sch
Aug 18, 2004 16:03 */
/* Automatically generated by hvveri version 9.6.2 Release Build2 */
`ifdef exemplar
`ifdef synthesis
example_en_16bit_a.vhd
-- VHDL Model Created from SCS Schematic example_en_16bit_a.sch
-- Aug 18, 2004 17:02
-- Automatically generated by vdvhdl version 9.6.2 Release Build2
library IEEE;
use IEEE.std_logic_1164
example_en_16bit_a.v
/* Verilog Model Created from SCS Schematic example_en_16bit_a.sch
Aug 18, 2004 17:02 */
/* Automatically generated by hvveri version 9.6.2 Release Build2 */
`ifdef exemplar
`ifdef synthesi
example_en_24bit_a.vhd
-- VHDL Model Created from SCS Schematic example_en_24bit_a.sch
-- Aug 18, 2004 17:55
-- Automatically generated by vdvhdl version 9.6.2 Release Build2
library IEEE;
use IEEE.std_logic_1164
example_en_24bit_a.v
/* Verilog Model Created from SCS Schematic example_en_24bit_a.sch
Aug 18, 2004 17:55 */
/* Automatically generated by hvveri version 9.6.2 Release Build2 */
`ifdef exemplar
`ifdef synthesi
example_en_32bit_a.vq
`timescale 1ps / 1ps
/* Verilog Header Created from SCS Schematic example_en_32bit_a.sch
Aug 14, 2003 11:13 */
module example_en_32bit_a( clear_in , clk_in, enable_in, count_out );
input
example_en_32bit_a.vhd
-- VHDL Model Created from SCS Schematic example_en_32bit_a.sch
-- Aug 18, 2004 18:06
-- Automatically generated by vdvhdl version 9.6.2 Release Build2
library IEEE;
use IEEE.std_logic_1164
example_en_32bit_a.vh
/* Verilog Header Created from SCS Schematic example_en_32bit_a.sch
Aug 14, 2003 11:13 */
module example_en_32bit_a( clear_in , clk_in, enable_in, count_out );
input clear_in, clk_in;
out
example_en_32bit_a.v
/* Verilog Model Created from SCS Schematic example_en_32bit_a.sch
Aug 18, 2004 18:06 */
/* Automatically generated by hvveri version 9.6.2 Release Build2 */
`ifdef exemplar
`ifdef synthesi
example_24bit_load.vh
/* Verilog Header Created from SCS Schematic example_24bit_load.sch
Aug 15, 2003 11:51 */
module example_24bit_load( clear_in , clk_in, data, enable_in, load_in, count_out );
input clear_in