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Schematic 的代码
csc_top.pcf
SCHEMATIC START ;
// created by map version E.38 on Fri Aug 02 15:08:03 2002
NET "Clock_ibuf/IBUFG" BEL "Clock_ibuf/BUFG.GLKMUX" USELOCALCONNECT ;
NET "Clock_ibuf/IBUFG" PERIOD = 12.500 nS HIGH
csc_top.pcf
SCHEMATIC START ;
// created by map version E.38 on Fri Aug 02 15:08:27 2002
NET "Clock_ibuf/IBUFG" BEL "Clock_ibuf/BUFG.GLKMUX" USELOCALCONNECT ;
NET "Clock_ibuf/IBUFG" PERIOD = 12.500 nS HIGH
csc_top.pcf
SCHEMATIC START ;
// created by map version E.38 on Fri Aug 02 15:06:53 2002
NET "Clock_ibuf/IBUFG" PERIOD = 12.500 nS HIGH 50.000000 % ;
TIMEGRP "Clock" = BEL "g[2]" BEL "g[3]" BEL "g[4]" BEL
csc_top.pcf
SCHEMATIC START ;
// created by map version E.38 on Fri Aug 02 15:09:26 2002
NET "Clock_ibuf/IBUFG" PERIOD = 12.500 nS HIGH 50.000000 % ;
TIMEGRP "Clock" = BEL "g[2]" BEL "g[3]" BEL "g[4]" BEL
csc_top.pcf
SCHEMATIC START ;
// created by map version E.38 on Fri Aug 02 15:10:58 2002
NET "Clock_ibuf/IBUFG" PERIOD = 12.500 nS HIGH 50.000000 % ;
TIMEGRP "Clock" = BEL "g[2]" BEL "g[3]" BEL "g[4]" BEL
cy3662.opj
(ExpressProject ""
(ProjectType "UNKNOWN")
(Folder "Design Resources"
(Folder "Library")
(File ".\cy3662.dsn"
(Type "Schematic Design"))
(BuildFileAddedOrDeleted "x")
moore_2.pcf
SCHEMATIC START ;
// created by map version D.19 on Fri Nov 08 10:25:49 2002
SCHEMATIC END ;
example_en_8bit_a.v
/* Verilog Model Created from SCS Schematic example_en_8bit_a.sch
Aug 18, 2004 16:49 */
/* Automatically generated by hvveri version 9.6.2 Release Build2 */
`ifdef exemplar
`ifdef synthesis
example_en_8bit_a.vhd
-- VHDL Model Created from SCS Schematic example_en_8bit_a.sch
-- Aug 18, 2004 16:49
-- Automatically generated by vdvhdl version 9.6.2 Release Build2
library IEEE;
use IEEE.std_logic_1164.
example_en_4bit.vhd
-- VHDL Model Created from SCS Schematic example_en_4bit.sch
-- Aug 13, 2003 12:31
-- Automatically generated by vdvhdl version 9.5 Release Build2
library IEEE;
use IEEE.std_logic_1164.all;