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count_4.sch
VERSION 6
BEGIN SCHEMATIC
BEGIN ATTR DeviceFamilyName "xc9500"
DELETE all:0
EDITNAME all:0
EDITTRAIT all:0
END ATTR
BEGIN NETLIST
BEGIN BLOCKDEF cd4
hao.sch
VERSION 6
BEGIN SCHEMATIC
BEGIN ATTR DeviceFamilyName "spartan3"
DELETE all:0
EDITNAME all:0
EDITTRAIT all:0
END ATTR
BEGIN NETLIST
BEGIN BLOCKDEF d
andnor2_p.vf
// Verilog model created from schematic andnor2_p.sch - Wed Nov 13 16:47:40 2002
`timescale 1ns / 1ps
module andnor2_p(in1, in2, in3, in4, in5, out_t);
input in1;
input in2;
input in3;
counter.pcf
SCHEMATIC START ;
// created by map version G.30 on Tue Oct 12 22:26:30 2004
SCHEMATIC END ;
useful-routines.ulp
#usage "Collection of useful routines\n"
""
"Author: support@cadsoft.de"
// THIS PROGRAM IS PROVIDED AS IS AND WITHOUT WARRANTY OF ANY KIND, EXPRESSED OR
goht_pb.rep
Protel Advanced Schematic Annotation Report for 'GoHT_PB' 11:00:56 8-Jul-2006
sample.rep
Protel Advanced Schematic Annotation Report for 'Sample.Sch' 11:21:30 30-Dec-2006
JP? => JP100
goht_mb.rep
Protel Advanced Schematic Annotation Report for 'GoHT_MB' 16:49:34 13-May-2007
goht_pb.rep
Protel Advanced Schematic Annotation Report for 'GoHT_PB' 11:00:56 8-Jul-2006
sample.rep
Protel Advanced Schematic Annotation Report for 'Sample.Sch' 11:21:30 30-Dec-2006
JP? => JP100