代码搜索结果

(ExpressProject "" (ProjectType "UNKNOWN") (Folder "Design Resources" (Folder "Library") (File ".\29as21.dsn" (Type "Schematic Design")) (BuildFileAddedOrDeleted "x")

(ExpressProject "" (ProjectType "PCB") (Folder "Design Resources" (Folder "Library") (File ".\8139dl-pci.dsn" (Type "Schematic Design")) (BuildFileAddedOrDeleted "x")

Protel Advanced Schematic Annotation Report for 'Sheet1.Sch' 00:04:44 18-May-2005 R? => R4 R? => R5 R? => R6 R? => R7 R?

Protel Advanced Schematic Annotation Report for 'Sheet1.Sch' 00:04:44 18-May-2005 R? => R4 R? => R5 R? => R6 R? => R7 R?

JDF B // Created by Version 2.0 PROJECT Simple 4x1 MUX - Mixed Sch/VHDL Design DESIGN mux4x1_mixed Normal DEVKIT ispLSI5256VE-165LT128 ENTRY Schematic/VHDL STIMULUS mux4x1.abv MODULE mux4x1.sc

EAGLE Version 4.11 Copyright (c) 1988-2003 CadSoft Electrical Rule Check for D:/c/EAGLE-4.11/projects/tof/675/untitled.sch at 4/05/2005 11:35:06a Board and schematic are consistent 0 err

Protel Advanced Schematic Annotation Report for 'cable.sch' 20:29:21 29-Jul-2002 J? => J1 R? => R1 R? => R2 R? => R3 R?

Synthesizing work.top.gen Synthesizing work.add.cell_level Synthesizing work.sum_gen.schematic @W:"syng0a01060":250:13:250:18|Unbound component LOGIC2 mapped to black box Synthesizing work.logic2.

SCHEMATIC START ; // created by map version G.28 on Wed Jun 13 11:02:20 2007 SCHEMATIC END ;

SCHEMATIC START ; // created by map version G.28 on Wed Jun 27 00:05:16 2007 COMP "time2" LOCATE = SITE "P89" LEVEL 1; COMP "time1" LOCATE = SITE "P61" LEVEL 1; COMP "time2" LOCATE =