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VERSION 6 BEGIN SCHEMATIC BEGIN ATTR DeviceFamilyName "virtex" DELETE all:0 EDITNAME all:0 EDITTRAIT all:0 END ATTR BEGIN NETLIST SIGNAL "outs(0)"

# Schematic : View VHDL Functional Model stopwatch.vhf stopwatch.cmd_log # Schematic : View VHDL Functional Model cnt60.vhf cnt60.cmd_log # XAW : View VHDL Source DCM1.vhd # Schematic : View V

-- Vhdl model created from schematic J:\eda\Xilinx\virtex2\data\drawing\ftce.sch - Thu Dec 19 18:12:07 2002 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; -- synopsys trans

SCHEMATIC START ; // created by map version F.23 on Thu Dec 19 18:12:20 2002 COMP "reset" LOCATE = SITE "A5" LEVEL 1; SCHEMATIC END ;

SCHEMATIC START ; // created by map version F.28 on Thu Mar 27 15:51:54 2003 COMP "modb_out" LOCATE = SITE "B6" LEVEL 1; COMP "top2a_c" LOCATE = SITE "A4" LEVEL 1; COMP "modb_clk_pad" LOCATE

SCHEMATIC START ; // created by map version F.28 on Thu Mar 27 15:47:31 2003 COMP "modb_out" LOCATE = SITE "B6" LEVEL 1; COMP "top2a_c" LOCATE = SITE "A4" LEVEL 1; COMP "modb_clk_pad" LOCATE

SCHEMATIC START ; // created by map version F.28 on Thu Mar 27 15:41:30 2003 COMP "top2a_c" LOCATE = SITE "A4" LEVEL 1; COMP "modb_clk_pad" LOCATE = SITE "D7" LEVEL 1; COMP "moda_data" LOCATE

SCHEMATIC START ; // created by map version F.28 on Thu Mar 27 16:07:52 2003 COMP "top2a_c" LOCATE = SITE "A4" LEVEL 1; COMP "modb_clk_pad" LOCATE = SITE "D7" LEVEL 1; COMP "dll_rst" LOCATE =

SCHEMATIC START ; // created by map version G.28 on Thu Jul 29 11:27:21 2004 SCHEMATIC END ;

SCHEMATIC START ; // created by map version G.23 on Fri Aug 25 16:10:44 2006 SCHEMATIC END ;