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找到约 2,153 项符合
Schematic 的代码
andnor2.vf
// Verilog model created from schematic andnor2.sch - Wed Nov 13 17:04:16 2002
`timescale 1ns / 1ps
module andnor2(in1, in2, in3, in4, out_t);
input in1;
input in2;
input in3;
input
mode7cnt.sch
VERSION 6
BEGIN SCHEMATIC
BEGIN ATTR DeviceFamilyName "virtexe"
DELETE all:0
EDITNAME all:0
EDITTRAIT all:0
END ATTR
BEGIN NETLIST
SIGNAL "clk"
top.pcf
SCHEMATIC START ;
// created by map version F.23 on Wed Nov 06 17:38:46 2002
NET "clkb_BUFGP/IBUFG" BEL "clkb_BUFGP/BUFG.GCLKMUX" USELOCALCONNECT ;
NET "clka_BUFGP/IBUFG" BEL "clka_BUFGP/BUFG.GCLK
top.pcf
SCHEMATIC START ;
// created by map version G.30 on Wed Jun 02 03:27:21 2004
NET "bufg_modb/IBUFG" BEL "bufg_modb/BUFG.GCLKMUX" USELOCALCONNECT ;
NET "bufg_modc/IBUFG" BEL "bufg_modc/BUFG.GCLKMUX"
stopwatch.vf
// Verilog model created from schematic stopwatch.sch - Thu Dec 05 17:54:29 2002
`timescale 1ns / 1ps
module stopwatch(clk, reset, strstop, onesout, tensout, tenthsout);
input clk;
input
outs3.vf
// Verilog model created from schematic outs3.sch - Thu Dec 05 17:54:29 2002
`timescale 1ns / 1ps
module outs3(inputs, outs);
input [9:0] inputs;
output [9:0] outs;
wire XLXN_12;
wire
cnt60.vf
// Verilog model created from schematic J:\eda\Xilinx\virtex2\data\drawing\ftce.sch - Thu Dec 05 17:54:30 2002
`timescale 1ns / 1ps
module FTCE_MXILINX_cnt60(C, CE, CLR, T, Q);
input C;
stopwatch.vf
// Verilog model created from schematic stopwatch.sch - Thu Dec 05 17:54:29 2002
`timescale 1ns / 1ps
module stopwatch(clk, reset, strstop, onesout, tensout, tenthsout);
input clk;
input
outs3.vf
// Verilog model created from schematic outs3.sch - Thu Dec 05 17:54:29 2002
`timescale 1ns / 1ps
module outs3(inputs, outs);
input [9:0] inputs;
output [9:0] outs;
wire XLXN_12;
wire
cnt60.vf
// Verilog model created from schematic J:\eda\Xilinx\virtex2\data\drawing\ftce.sch - Thu Dec 05 17:54:30 2002
`timescale 1ns / 1ps
module FTCE_MXILINX_cnt60(C, CE, CLR, T, Q);
input C;