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找到约 2,153 项符合
Schematic 的代码
mylibrary.opj
(ExpressProject ""
(ProjectVersion "19981106")
(ProjectType "PCB")
(Folder "Design Resources"
(Folder "Library")
(File ".\mylibrary.olb"
(Type "Schematic Library"))
(Bui
myproj.opj
(ExpressProject "myproj"
(ProjectVersion "19981106")
(ProjectType "PCB")
(Folder "Design Resources"
(Folder "Library")
(NoModify)
(File ".\myproj.dsn"
(Type "Schematic D
schcvt.ini
[General]
Default Input=OrCAD Capture
Default Output=PADS Logic
[Protel 99SE/DXP -> PADS Logic - General]
Config File=D:\sfot\电子类\Translators\Schematic\protel2pl.cnv
[Protel 99SE/DXP -> PADS Logi
aquisition_test.gfl
# VHDL : Create Schematic Symbol
__projnav/tb.rsp
acquistion.spl
__projnav/vhd2spl.err
# VHDL : Create Schematic Symbol
__projnav/tb.rsp
acquistion.spl
__projnav/vhd2spl.err
# XST (Creating Ls
horse.sdf
ISIS SCHEMATIC DESCRIPTION FORMAT 6.1
=====================================
Design: E:\罗兵\学习资料\Proteus\跑马灯\horse.dsn
Doc. no.:
Revision:
Author:
Created: 06/08/02
Modified: 0
top_sh4.sch
VERSION 6
BEGIN SCHEMATIC
BEGIN ATTR DeviceFamilyName "virtex2"
DELETE all:0
EDITNAME all:0
EDITTRAIT all:0
END ATTR
BEGIN NETLIST
SIGNAL xr15(7:0)
top_sh3.sch
VERSION 6
BEGIN SCHEMATIC
BEGIN ATTR DeviceFamilyName "virtex2"
DELETE all:0
EDITNAME all:0
EDITTRAIT all:0
END ATTR
BEGIN NETLIST
SIGNAL xr2(7:0)
ufpga2.v
module Ufpga2 (
clock48,
rcvin, // usbrcv on lg schematic
vpin,
vmin,
vmo,
vpo,
usboen,
usbclockout,
usbclock,
pwro
top.pcf
SCHEMATIC START ;
// created by map version G.28 on Fri Dec 15 10:35:27 2006
COMP "addr_SRAM" LOCATE = SITE "P203" LEVEL 1;
COMP "addr_SRAM" LOCATE = SITE "P200" LEVEL 1;
COMP "addr_SRA
top.sch
VERSION 6
BEGIN SCHEMATIC
BEGIN ATTR DeviceFamilyName "spartan3"
DELETE all:0
EDITNAME all:0
EDITTRAIT all:0
END ATTR
BEGIN NETLIST
SIGNAL clk