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# Schematic : PDCL (jhdparse) # Schematic : PDCL (jhdparse) # Schematic : PDCL (jhdparse) # Schematic : PDCL (jhdparse) # Schematic : View Verilog Functional Model andnor2.vf # Schematic : View

Checking Pins and Pin Connections -------------------------------------------------- Checking Schematic: SCHEMATIC1 -------------------------------------------------- Checking Electrical Rules

Protel Advanced Schematic Annotation Report for 'Sheet1.Sch' 17:43:44 12-Mar-2004 C? => C8 C? => C9 C? => C10 C? => C11

(ExpressProject "" (ProjectVersion "19981106") (ProjectType "PCB") (Folder "Design Resources" (Folder "Library") (File ".\amcc405ep1.1_release.dsn" (Type "Schematic Design"))

VERSION 6 BEGIN SCHEMATIC BEGIN ATTR DeviceFamilyName "xc9500" DELETE all:0 EDITNAME all:0 EDITTRAIT all:0 END ATTR BEGIN NETLIST BEGIN BLOCKDEF cd4

SCHEMATIC START ; // created by map version G.38 on Tue Jun 26 13:01:19 2007 NET "CLK_IN_BUFGP/IBUFG" BEL "CLK_IN_BUFGP/BUFG.GCLKMUX" USELOCALCONNECT ; SCHEMATIC END ;

SCHEMATIC START ; // created by map version G.38 on Tue Jun 26 12:51:21 2007 NET "SCLK_BUFGP/IBUFG" BEL "SCLK_BUFGP/BUFG.GCLKMUX" USELOCALCONNECT ; SCHEMATIC END ;

SCHEMATIC START ; // created by map version G.38 on Tue Jun 26 13:05:41 2007 NET "SCLK_BUFGP/IBUFG" BEL "SCLK_BUFGP/BUFG.GCLKMUX" USELOCALCONNECT ; SCHEMATIC END ;

SCHEMATIC START ; // created by map version G.38 on Tue Jun 26 13:03:36 2007 NET "SCLK_BUFGP/IBUFG" BEL "SCLK_BUFGP/BUFG.GCLKMUX" USELOCALCONNECT ; SCHEMATIC END ;

Version 1.0.1 01-11-2002 - changed jtag port to : pind - changed baudrate setting to 115200 - changed and completed schematic diagram - added docs and READMEs - added results directory - added