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* source PARA V_Vi1 N00116 0 +PULSE 0 10 2us 2us 2us 2us 8us R_R2 N00116 VC {rval} C_C1 0 VC 1n .PARAM rval=1k

.ALIASES V_V1 V1(+=N00110 -=0 ) V_V4 V4(+=N00632 -=0 ) R_R1 R1(1=N00110 2=0 ) R_R2 R2(1=N00632 2=0 ) V_V3 V3(+=N02839 -=0 ) R_R3

* source TRAN V_V1 N00110 0 +SIN 0 5 1000 0 0 0 V_V4 N00632 0 +PULSE 0 10 2us 2us 2us 2us 8us R_R1 N00110 0 1k R_R2 N00632 0 1k V_V3 N02839 0

.ALIASES V_V1 V1(+=N00452 -=0 ) R_R1 R1(1=N00452 2=VC2 ) C_C1 C1(1=VC2 2=0 ) _ _(Vc2=VC2) .ENDALIASES

* source TEMP V_V1 N00452 0 +PULSE 0V 10V 2us 2us 2us 2us 8us R_R1 N00452 VC2 Rbreak 20 C_C1 VC2 0 Cbreak 1n

.ALIASES V_V1 V1(+=N00118 -=0 ) R_R1 R1(1=N00118 2=OUT ) R_R2 R2(1=0 2=OUT ) R_R3 R3(1=N00880 2=N00914 ) R_R4 R4(1=VO 2=N00994 ) V_V2

* source NOSIE V_V1 N00118 0 DC 0Vdc AC 1Vac R_R1 N00118 OUT 1k R_R2 0 OUT 1k R_R3 N00880 N00914 75k R_R4 VO N00994 1k V_V2 N00880 0

(ExpressProject "" (ProjectVersion "19981106") (ProjectType "PCB") (Folder "Design Resources" (Folder "Library") (File ".\s1649a_schematic.dsn" (Type "Schematic Design"))

Record=TopLevelDocument|FileName=PAGE01.SchDoc

[Design] Version=1.0 HierarchyMode=0 ChannelRoomNamingStyle=0 OutputPath= ChannelDesignatorFormatString=$Component_$RoomName ChannelRoomLevelSeperator=_ OpenOutputs=1 ArchiveProject=0 Timesta