代码搜索结果

SCHEMATIC START ; // created by map version G.28 on Fri Feb 24 02:12:33 2006 COMP "A" LOCATE = SITE "P163" LEVEL 1; COMP "A" LOCATE = SITE "P161" LEVEL 1; COMP "A" LOCATE = SITE "P1

SCHEMATIC START ; // created by map version G.28 on Fri Feb 24 01:48:55 2006 COMP "OUT" LOCATE = SITE "P33" LEVEL 1; COMP "OUT" LOCATE = SITE "P30" LEVEL 1; COMP "OUT" LOCATE = SITE

ISIS SCHEMATIC DESCRIPTION FORMAT 6.1 ===================================== Design: G:\Benny的文档\Proteus\点阵LED\点阵LED(梅川酷子)\滚动显示汉字(梅川酷子)\滚动显示屏.DSN Doc. no.: Revision: Author: Cr

SCHEMATIC START ; // created by map version E.38 on Thu Dec 16 10:16:03 2004 COMP "dataport" LOCATE = SITE "P10" LEVEL 1; COMP "xrd" LOCATE = SITE "P71" LEVEL 1; COMP "clk" LOCATE = SITE "P9

SCHEMATIC START ; // created by map version G.30 on Wed Jun 02 03:27:21 2004 NET "bufg_modb/IBUFG" BEL "bufg_modb/BUFG.GCLKMUX" USELOCALCONNECT ; NET "bufg_modc/IBUFG" BEL "bufg_modc/BUFG.GCLKMUX"

ISIS SCHEMATIC DESCRIPTION FORMAT 6.1 ===================================== Design: G:\单片机小组\DS1302时钟+DS18B20+无线遥控应用程序\DS1302.DSN Doc. no.: Revision: Author: Created: 0

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SCHEMATIC START ; // created by map version E.35 on Tue Dec 17 10:05:37 2002 COMP "ck" LOCATE = SITE "P113" LEVEL 1; COMP "clk" LOCATE = SITE "P213" LEVEL 1; COMP "ck_x" LOCATE = SITE "P114" LE

// Verilog model created from schematic outs3.sch - Thu Dec 05 17:54:29 2002 `timescale 1ns / 1ps module outs3(inputs, outs); input [9:0] inputs; output [9:0] outs; wire XLXN_12; wire

// Verilog model created from schematic J:\eda\Xilinx\virtex2\data\drawing\ftce.sch - Thu Dec 05 17:54:30 2002 `timescale 1ns / 1ps module FTCE_MXILINX_cnt60(C, CE, CLR, T, Q); input C;