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SCHEMATIC START ; # map: version ispLever_v51_Alpha_Build (35) -- WARNING: Map write only section -- Thu Jul 14 10:14:49 2005 SYSCONFIG PERSISTENT=OFF CONFIG_MODE=SLAVE_SERIAL DONE_OD=ON DONE_EX=

SCHEMATIC START ; # map: version ispLever_v50_Production_Build (40) -- WARNING: Map write only section -- Thu Jul 21 15:03:12 2005 SYSCONFIG PERSISTENT=OFF CONFIG_MODE=JTAG DONE_OD=ON DONE_EX=OFF M

/* Verilog Header Created from SCS Schematic example_en_32bit_a.sch Aug 14, 2003 11:13 */ module example_en_32bit_a( clear_in , clk_in, enable_in, count_out ); input clear_in, clk_in; out

/* Verilog Header Created from SCS Schematic example_24bit_load.sch Aug 15, 2003 11:51 */ module example_24bit_load( clear_in , clk_in, data, enable_in, load_in, count_out ); input clear_in

/* Verilog Header Created from SCS Schematic example_8bit_load.sch Aug 15, 2003 10:40 */ module example_8bit_load( clear_in , clk_in, data, enable_in, load_in, count_out ); input clear_in,

/* Verilog Header Created from SCS Schematic example_16bit_load.sch Aug 15, 2003 11:19 */ module example_16bit_load( clear_in , clk_in, data, enable_in, load_in, count_out ); input clear_in

/* Verilog Header Created from SCS Schematic example_32bit_load.sch Aug 15, 2003 13:22 */ module example_32bit_load( clear_in , clk_in, data, enable_in, load_in, count_out ); input clear_in

/* Verilog Header Created from SCS Schematic example_4bit_load.sch Aug 15, 2003 10:23 */ module example_4bit_load( clear_in , clk_in, data, enable_in, load_in, count_out ); input clear_in,

SCHEMATIC START ; // created by map version E.38 on Wed Dec 15 20:47:03 2004 COMP "portout" LOCATE = SITE "P232" LEVEL 1; COMP "portout" LOCATE = SITE "P231" LEVEL 1; COMP "portout"

ISIS SCHEMATIC DESCRIPTION FORMAT 6.1 ===================================== Design: I:\电信0502单片机课设\电子万年历\DS1302.DSN Doc. no.: Revision: Author: Created: 05/09/19 Modif