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stopwatch.vf
// Verilog model created from schematic stopwatch.sch - Thu Dec 05 17:54:29 2002
`timescale 1ns / 1ps
module stopwatch(clk, reset, strstop, onesout, tensout, tenthsout);
input clk;
input
lisa1.sdf
ISIS SCHEMATIC DESCRIPTION FORMAT 6.1
=====================================
Design: E:\zhou\模拟比赛\相关资料\PWM资料\PD口输出PWM波\pwm.DSN
Doc. no.:
Revision:
Author:
Created: 05/05
stopwatch.vf
// Verilog model created from schematic stopwatch.sch - Thu Dec 05 17:54:29 2002
`timescale 1ns / 1ps
module stopwatch(clk, reset, strstop, onesout, tensout, tenthsout);
input clk;
input
stopwatch.vf
// Verilog model created from schematic stopwatch.sch - Thu Dec 05 17:54:29 2002
`timescale 1ns / 1ps
module stopwatch(clk, reset, strstop, onesout, tensout, tenthsout);
input clk;
input
20-5b.pdf
{COMPONENT C:\DOCUMENTS AND SETTINGS\H\桌面\20-5\20-5B.SYM
{ENVIRONMENT
{PDIFvrev 3.00}
{Program "CUPL(WM) Version 5.0a"}
{DBtype "Schematic"}
{DBvrev 1.01}
{DBtime "Fri Aug 18 21:17:
20-5.pdf
{COMPONENT C:\DOCUMENTS AND SETTINGS\H\桌面\20-5\20-5.SYM
{ENVIRONMENT
{PDIFvrev 3.00}
{Program "CUPL(WM) Version 5.0a"}
{DBtype "Schematic"}
{DBvrev 1.01}
{DBtime "Fri Aug 18 20:54:4
lisa1.sdf
ISIS SCHEMATIC DESCRIPTION FORMAT 6.1
=====================================
Design: F:\单片机\做好的项目\项目（下载）.C\播放音乐\PlayMusic.DSN
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Author:
Created: 05/09/
playmusic.sdf
ISIS SCHEMATIC DESCRIPTION FORMAT 6.1
=====================================
Design: F:\单片机\源程序\播放音乐\PlayMusic.DSN
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Author:
Created: 05/09/17
Modified: 06/0
lisa1.sdf
ISIS SCHEMATIC DESCRIPTION FORMAT 6.1
=====================================
Design: F:\avr\AVR与PROTEUS应用\新型AVR单片机应用\ad_da\exp2.DSN
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Created:
lisa1.sdf
ISIS SCHEMATIC DESCRIPTION FORMAT 6.1
=====================================
Design: F:\proteus\8051单片机\DS1302时钟\DS1302.DSN
Doc. no.:
Revision:
Author:
Created: 05/09/19