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SCHEMATIC START ; // created by map version F.25 on Sat Dec 07 16:30:18 2002 SCHEMATIC END ;

SCHEMATIC START ; // created by map version F.25 on Sat Dec 07 15:49:26 2002 SCHEMATIC END ;

SCHEMATIC START ; // created by map version F.25 on Sat Dec 28 11:52:12 2002 COMP "reset" LOCATE = SITE "L26" LEVEL 1; TIMEGRP "clk" = BEL "counter_2" BEL "counter_3" BEL "counter_4" BEL "counte

SCHEMATIC START ; // created by map version F.25 on Sat Dec 28 15:56:06 2002 COMP "reset" LOCATE = SITE "L26" LEVEL 1; TIMEGRP "clk" = BEL "counter_2" BEL "counter_3" BEL "counter_4" BEL "counte

SCHEMATIC START ; // created by map version G.30 on Tue Oct 12 22:27:24 2004 SCHEMATIC END ;

// Verilog model created from schematic andnor2_p.sch - Wed Nov 13 16:47:40 2002 `timescale 1ns / 1ps module andnor2_p(in1, in2, in3, in4, in5, out_t); input in1; input in2; input in3;

# Schematic : PDCL (jhdparse) # Schematic : PDCL (jhdparse) # Schematic : PDCL (jhdparse) # Schematic : PDCL (jhdparse) # Schematic : View Verilog Functional Model andnor2.vf # Schematic : View

// Verilog model created from schematic andnor2.sch - Wed Nov 13 17:04:16 2002 `timescale 1ns / 1ps module andnor2(in1, in2, in3, in4, out_t); input in1; input in2; input in3; input

SCHEMATIC START ; // created by map version F.23 on Wed Nov 06 17:38:46 2002 NET "clkb_BUFGP/IBUFG" BEL "clkb_BUFGP/BUFG.GCLKMUX" USELOCALCONNECT ; NET "clka_BUFGP/IBUFG" BEL "clka_BUFGP/BUFG.GCLK

SCHEMATIC START ; // created by map version G.30 on Tue Oct 12 22:26:30 2004 SCHEMATIC END ;