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The schematic is at foler schematic. The hex file is at foler default. You can compiler the code yourself using AvrStudio4.13 b528 + WinAVR20070122

JDF B // Created by Version 3.0 PROJECT Untitled DESIGN trafic Normal DEVKIT ispLSI1032E-70LJ84 ENTRY Schematic/VHDL MODULE trafic.vhd MODSTYLE trafic Normal SYNTHESIS_TOOL Synplify

Checking Pins and Pin Connections -------------------------------------------------- Checking Schematic: SCHEMATIC1 -------------------------------------------------- Checking Electrical Rules

Checking Pins and Pin Connections -------------------------------------------------- Checking Schematic: SCHEMATIC1 -------------------------------------------------- Checking Electrical Rules

Synthesizing work.top.gen Synthesizing work.add.cell_level Synthesizing work.sum_gen.schematic @W:"syng0a01060":250:13:250:18|Unbound component LOGIC2 mapped to black box Synthesizing work.logic2.

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