代码搜索结果

SYNOPSYS = get_unix_variable("SYNOPSYS") generic_symbol_library = {generic.sdb}; search_path = {. SYNOPSYS + "/libraries/syn" \ SYNOPSYS + "/packages/IEEE/lib" \ ./db \ ./src \ ./scripts}

Output: Protel Type : ProtelNetlist From : Project [MCU.PrjPCB] Generated File[MCU.NET] Output: Schematic Prints Type : Schematic Print From : Schematic Document [mcu.SchDoc] Printe

# Schematic : PDCL (jhdparse) __projnav/acquisition_jhdparse_tcl.rsp # Schematic : PDCL (jhdparse) __projnav/dig_osc_jhdparse_tcl.rsp # Schematic : PDCL (jhdparse) __projnav/vga_display_jhdparse_

# Schematic : PDCL (jhdparse) __projnav/acquisition_jhdparse_tcl.rsp # Schematic : PDCL (jhdparse) __projnav/dig_osc_jhdparse_tcl.rsp # Schematic : PDCL (jhdparse) __projnav/vga_display_jhdparse_

JB8 DES Key Hardware Files Description jb8_deskey_sch_rev00.pdf - Schematic jb8_deskey_pcb_top.pdf - pcb top silk screen jb8_deskey_pcb_bot.pdf - pcb bottom silk screen jb8_deskey_gerbe

Date and Time : 06/28/12 21:34:36 -------------------------------------------------- Checking Schematic: SCHEMATIC1 -------------------------------------------------- Checking Electrical Rules

Date and Time : 06/28/12 21:34:36 -------------------------------------------------- Checking Schematic: SCHEMATIC1 -------------------------------------------------- Checking Electrical Rules

# Schematic : PDCL (jhdparse) __projnav/top_jhdparse_tcl.rsp # Schematic : PDCL (jhdparse) __projnav/top_jhdparse_tcl.rsp # VHDL : Create Schematic Symbol __projnav/tb.rsp adecode.spl __projnav

# Schematic : PDCL (jhdparse) __projnav/top_jhdparse_tcl.rsp # Schematic : PDCL (jhdparse) __projnav/top_jhdparse_tcl.rsp # VHDL : Create Schematic Symbol __projnav/tb.rsp adecode.spl __projnav

# Schematic : PDCL (jhdparse) __projnav/top_jhdparse_tcl.rsp # Schematic : PDCL (jhdparse) __projnav/top_jhdparse_tcl.rsp # VHDL : Create Schematic Symbol __projnav/tb.rsp adecode.spl __projnav