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Schematic 的代码
traplog.tlg
Synthesizing work.top.gen
Synthesizing work.add.cell_level
Synthesizing work.sum_gen.schematic
@W:"syng0a01060":250:13:250:18|Unbound component LOGIC2 mapped to black box
Synthesizing work.logic2.
krtlcd.pcf
SCHEMATIC START ;
// created by map version G.26 on Fri Jun 11 14:14:39 2004
COMP "lcd_dir" LOCATE = SITE "E22" LEVEL 1;
COMP "lcd_rst" LOCATE = SITE "E21" LEVEL 1;
COMP "lcd_e" LOCATE = SIT
xstdemo_vhdl_prj.gfl
# VHDL : PDCL (jhdparse)
__projnav/cnt_vhd_jhdparse_tcl.rsp
# Check Syntax
cnt_vhd2.stx
# xst flow : RunXST
cnt_vhd2.syr
cnt_vhd2.ngr
cnt_vhd2.prj
cnt_vhd2.sprj
cnt_vhd2.ana
cnt_vhd2.stx
cn
adi_deserializer.npl
JDF G
// Created by Project Navigator ver 1.0
PROJECT ADI_Deserializer
DESIGN adi_deserializer
DEVFAM virtex2
DEVFAMTIME 0
DEVICE xc2v250
DEVICETIME 0
DEVPKG fg256
DEVPKGTIME 0
DEVSPEED -5
mycpu.map.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info:
music.fit.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartu
mycpu.map.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info:
dianzheng.gfl
# VHDL : Create Schematic Symbol
__projnav/tb.rsp
chw.spl
__projnav/vhd2spl.err
# VHDL : Create Schematic Symbol
__projnav/tb.rsp
cnta.spl
__projnav/vhd2spl.err
# VHDL : Create Schematic Symbo
prescale_counter.pcf
SCHEMATIC START ;
// created by map version F.25 on Sat Dec 28 11:52:12 2002
COMP "reset" LOCATE = SITE "L26" LEVEL 1;
TIMEGRP "clk" = BEL "counter_2" BEL "counter_3" BEL "counter_4" BEL "counte
prescale_counter.pcf
SCHEMATIC START ;
// created by map version F.25 on Sat Dec 28 15:56:06 2002
COMP "reset" LOCATE = SITE "L26" LEVEL 1;
TIMEGRP "clk" = BEL "counter_2" BEL "counter_3" BEL "counter_4" BEL "counte