代码搜索：SW1
找到约 309 项符合「SW1」的源代码
代码结果 309
www.eeworm.com/read/18055/772727
v date_main.v
module date_main(
day_EN,
date_disp_clk,
Date_Set_EN,
Date_EN,
SW1,
SW2,
day0,
day1,
Disp_select_date,
month0,
month1
);
input day_EN;
input date_disp_clk;
input Date_Set_E
www.eeworm.com/read/290131/8503075
v control.v
module control(EN_in,SW1,RST,Red1,Red2,Yellow1,Yellow2,Green1,Green2);
output Red1;
output Red2;
output Yellow1;
output Yellow2;
output Green1;
output Green2;
input [1:0] EN_in;
input
www.eeworm.com/read/372977/9483143
v 复件 lcd_init(带ＴＰrd05）.v
//7.5 dotclk=1/8 clock 3.3M
module lcd_283rb06(cs,sclk,sdi,clock,hsync,vsync,enable,dotclk,
red,green,blue,A,sw2,ce,oe,we,sw1,sdao,sclo,penirq,db18,db19,db20,db21,db22,db23);
output reg cs
www.eeworm.com/read/372977/9483169
v lcd_init_0707.v
//7.5 dotclk=1/8 clock 3.3M
module lcd_283rb06(cs,sclk,sdi,clock,hsync,vsync,enable,dotclk,
red,green,blue,A,sw4,ce,oe,we,sw1,sdao,sclo,penirq,db18,db19,db20,db21,db22,db23);
output reg cs
www.eeworm.com/read/372977/9483178
v 复件 复件 lcd_init(带ＴＰrd05）.v
//7.5 dotclk=1/8 clock 3.3M
module lcd_283rb06(cs,sclk,sdi,clock,hsync,vsync,enable,dotclk,
red,green,blue,A,sw2,ce,oe,we,sw1,sdao,sclo,penirq,db18,db19,db20,db21,db22,db23);
output reg cs
www.eeworm.com/read/372977/9483182
v lcd_init(rb07).v
//7.5 dotclk=1/8 clock 3.3M
module lcd_283rb06(cs,sclk,sdi,clock,hsync,vsync,enable,dotclk,
red,green,blue,A,sw2,ce,oe,we,sw1,sdao,sclo,penirq,db18,db19,db20,db21,db22,db23);
output reg cs
www.eeworm.com/read/364872/9889345
v oc8051_fpga_top.v
// synopsys translate_off
`include "oc8051_timescale.v"
// synopsys translate_on
module oc8051_fpga_top (clk, rst, int1, int2, int3, sw1, sw2, sw3, sw4, int_act, dispout, p0_out, p1_out, p2_out,
www.eeworm.com/read/361328/10057787
v gate_control.v
module gate_control(
SW0,SW1,SW2,
f1hz,f10hz,f100hz,
Latch_EN,
Counter_Clr,
Counter_EN,
dp_s1hz,dp_s10hz,dp_s100hz
);
output Latch_EN;
output Counter_Clr;
www.eeworm.com/read/273954/10893190
v control.v
module control(EN_in,SW1,RST,Red1,Red2,Yellow1,Yellow2,Green1,Green2);
output Red1;
output Red2;
output Yellow1;
output Yellow2;
output Green1;
output Green2;
input [1:0] EN_in;
input
www.eeworm.com/read/273951/10893495
v gate_control.v
module gate_control(
SW0,SW1,SW2,
f1hz,f10hz,f100hz,
Latch_EN,
Counter_Clr,
Counter_EN,
dp_s1hz,dp_s10hz,dp_s100hz
);
output Latch_EN;
output Counter_Clr;