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www.eeworm.com/read/145313/12736086

txt 移位寄存器：74164.txt

-- TTL164 Shift Register -- download from: www.fpga.com.cn & www.pld.com.cn library IEEE; use IEEE.Std_logic_1164.all; ENTITY dev164 IS PORT(a, b, nclr, clock : IN BIT; q : BUFFE
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www.eeworm.com/read/145313/12736117

vhd 简单的12位寄存器.vhd

-- User-Defined Macrofunction -- Download from: http://www.fpga.com.cn Library IEEE ; use IEEE.std_logic_1164.all ; ENTITY reg12 IS PORT( d : IN BIT_VECTOR(11 DOWNTO 0); clk :
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www.eeworm.com/read/145129/12752239

txt 移位寄存器：74164.txt

-- TTL164 Shift Register -- download from: www.fpga.com.cn & www.pld.com.cn library IEEE; use IEEE.Std_logic_1164.all; ENTITY dev164 IS PORT(a, b, nclr, clock : IN BIT; q : BUFFE
·
www.eeworm.com/read/145129/12752268

vhd 简单的12位寄存器.vhd

-- User-Defined Macrofunction -- Download from: http://www.fpga.com.cn Library IEEE ; use IEEE.std_logic_1164.all ; ENTITY reg12 IS PORT( d : IN BIT_VECTOR(11 DOWNTO 0); clk :
·
www.eeworm.com/read/145059/12754547

txt 移位寄存器：74164.txt

-- TTL164 Shift Register -- download from: www.fpga.com.cn & www.pld.com.cn library IEEE; use IEEE.Std_logic_1164.all; ENTITY dev164 IS PORT(a, b, nclr, clock : IN BIT; q : BUFFE
·
www.eeworm.com/read/145059/12754571

vhd 简单的12位寄存器.vhd

-- User-Defined Macrofunction -- Download from: http://www.fpga.com.cn Library IEEE ; use IEEE.std_logic_1164.all ; ENTITY reg12 IS PORT( d : IN BIT_VECTOR(11 DOWNTO 0); clk :
·
www.eeworm.com/read/141282/13024738

txt 移位寄存器：74164.txt

-- TTL164 Shift Register -- download from: www.fpga.com.cn & www.pld.com.cn library IEEE; use IEEE.Std_logic_1164.all; ENTITY dev164 IS PORT(a, b, nclr, clock : IN BIT; q : BUFFE
·
www.eeworm.com/read/141282/13024752

txt 简单的12位寄存器.txt

-- MAX+plus II VHDL Example -- User-Defined Macrofunction -- Copyright (c) 1994 Altera Corporation Library IEEE ; use IEEE.std_logic_1164.all ; ENTITY reg12 IS PORT( d : IN BIT_VECT
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www.eeworm.com/read/319921/13439505

txt 移位寄存器：74164.txt

-- TTL164 Shift Register -- download from: www.fpga.com.cn & www.pld.com.cn library IEEE; use IEEE.Std_logic_1164.all; ENTITY dev164 IS PORT(a, b, nclr, clock : IN BIT; q : BUFFE
·
www.eeworm.com/read/319921/13439528

txt 简单的12位寄存器.txt

-- User-Defined Macrofunction -- Download from: http://www.fpga.com.cn Library IEEE ; use IEEE.std_logic_1164.all ; ENTITY reg12 IS PORT( d : IN BIT_VECTOR(11 DOWNTO 0); clk :
·