代码搜索：SPCE
找到约 5,520 项符合「SPCE」的源代码
代码结果 5,520
www.eeworm.com/read/314989/13554648
c key_lpt.c
#include
#define P_Flash_Ctrl (volatile unsigned int *)(0x7555)
unsigned int press_key_lpt() //A口低八为并行键盘所用
{
unsigned int temp;
*P_IOA_Dir|=0x000f;
*P_IOA_Attrib|=0x00f
www.eeworm.com/read/348075/11613714
c isr.c
#include"spce061a.h"
unsigned int g_uiTime1,g_uiTime2;
void IRQ3(void)__attribute__((ISR));
void IRQ3(void)
{
if(*P_INT_Ctrl&0x0001)
{
g_uiTime2+=1;
if(g_uiTime2
www.eeworm.com/read/230436/14289141
c zuo.c
#include "SPCE061A.h"
unsigned int data_out1;
unsigned int key_in[16]={4,5,6,7,12,13,14,15,20,21,22,23,28,29,30,31};
unsigned int key_out[17]={"1234567890abcdef"}; // {"159C260D37AE48BF"};
//c
www.eeworm.com/read/9554/170259
sim ex36_zigbee.sim
[ARCH]
PROJ=SPCE3200
CPU=s+core
ISA=Score7
ENDIAN=0
ICE_SR=probe_dsr_general_s7_eb.hex8
TLB_LOG_ENTRY=0
Has Coprocessor1=0
Has Coprocessor2=0
Has Coprocessor3=0
[CACHE]
ICACHE_LINES=7
ICAC
www.eeworm.com/read/13747/282078
sim ex35_gprs.sim
[ARCH]
PROJ=SPCE3200
CPU=s+core
ISA=Score7
ENDIAN=0
ICE_SR=probe_dsr_general_s7_eb.hex8
TLB_LOG_ENTRY=0
Has Coprocessor1=0
Has Coprocessor2=0
Has Coprocessor3=0
[CACHE]
ICACHE_LINES=7
ICAC
www.eeworm.com/read/473745/1397351
c watchdog.c
#include "SPCE061.h"
#define count0 0xffffff;
#define count1 0xfff;
int main()
{
unsigned long int Delay;
//设置B口为同相低电平输出
*P_IOA_Dir =0xffff;
*P_IOA_Attrib =0xffff;
*P_IOA_Data =0;
www.eeworm.com/read/331810/3403546
asm more_int.asm
//=================================================================================
//来源： 《SPCE061单片机原理及应用技术》 第五章 中断系统
//描述： FIQ有FIQ_PWM、FIQ_TMA和FIQ_TMB三个中断源,当定时器A或B
// 计满溢出时产生中断请求信
www.eeworm.com/read/436051/1855289
c dac.c
#include "SPCE061V004.H"
#define Set_IOA_Bit(x) (*P_IOA_Data = *P_IOA_Buffer | x)
#define Clear_IOA_Bit(x) (*P_IOA_Data = *P_IOA_Buffer & ~x)
#define DIN 0x0001 //串行数据输入 IOA0
#define S
www.eeworm.com/read/436051/1855427
c menu.c
extern wavedata[8];
#include "SPCE061V004.H"
#include "lcd.h"
#include "menu.h"
//#define up 0x01
//#define down 0x10
//#define right 0x40
//#define relf 0x20
//#define 0k 0x02
//按键up:0
www.eeworm.com/read/397399/2402830
sim usb.sim
[ARCH]
PROJ=SPCE3200
CPU=s+core
ISA=Score7
ENDIAN=0
ICE_SR=probe_dsr_general_s7_eb.hex8
TLB_LOG_ENTRY=0
Has Coprocessor1=0
Has Coprocessor2=0
Has Coprocessor3=0
[CACHE]
ICACHE_LINES=7
ICAC