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Assembler report for gate_control Mon Jul 17 20:29:24 2006 Version 4.2 Build 157 12/07/2004 SJ Full Version --------------------- ; Table of Contents ; --------------------- 1. Legal Notic

--A1L32 is fref~100 at LC9 A1L32_p1_out = SW1 & f10hz; A1L32_p2_out = !SW1 & f1hz; A1L32_or_out = A1L32_p1_out # A1L32_p2_out; A1L32 = A1L32_or_out; --A1L22 is fref~94 at LC8 A1L22_p1_out =

Simulator report for gate_control Mon Jul 17 20:33:15 2006 Version 4.2 Build 157 12/07/2004 SJ Full Version --------------------- ; Table of Contents ; --------------------- 1. Legal Notic

Analysis & Synthesis report for gate_control Mon Jul 17 20:29:14 2006 Version 4.2 Build 157 12/07/2004 SJ Full Version --------------------- ; Table of Contents ; --------------------- 1.

-------------------------------------------------------------------------------------- Timing Analyzer Summary --------------------------------------------------------------------------------------

--A1L91 is fref~100 A1L91_p1_out = SW1 & f10hz; A1L91_p2_out = !SW1 & f1hz; A1L91_or_out = A1L91_p1_out # A1L91_p2_out; A1L91 = A1L91_or_out; --A1L81 is fref~94 A1L81_p1_out = SW2 & f100hz;

Timing Analyzer report for gate_control Mon Jul 17 20:29:32 2006 Version 4.2 Build 157 12/07/2004 SJ Full Version --------------------- ; Table of Contents ; --------------------- 1. Legal

Fitter report for gate_control Mon Jul 17 20:29:19 2006 Version 4.2 Build 157 12/07/2004 SJ Full Version --------------------- ; Table of Contents ; --------------------- 1. Legal Notice

Flow Status : Successful - Mon Jul 17 20:29:19 2006 Quartus II Version : 4.2 Build 157 12/07/2004 SJ Full Version Revision Name : gate_control Top-level Entity Name : gate_control Family : MAX7000

|gate_control SW0 => always0~0.IN0 SW1 => comb~0.IN0 SW1 => fref~0.OUTPUTSELECT SW1 => dp_s10hz~0.DATAA SW1 => always0~0.IN1 SW2 => comb~3.IN0 SW2 => fref~1.OUTPUTSELECT SW2 => dp_s1hz~0.OUTPU