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#Build: Synplify Pro 8.8, Build 008R, Dec 7 2006 #install: Y:\XILI\Synplify_8_8\fpga_88 #OS: Windows 2000 5.0 #Hostname: SJC-XILISTG1 #Implementation: verilog #Fri Mar 16 10:45:36 2007 $

fsm_encoding {10288281} onehot fsm_state_encoding {10288281} init {000000000001} fsm_state_encoding {10288281} waiting {000000000010} fsm_state_encoding {10288281} st_rd_cha {000000000100}

# # Synplicity Verification Interface File # Generated using Synplify-pro # # Copyright (c) 1996-2005 Synplicity, Inc. # All rights reserved # # Set logfile options vif_set_result_file data

NET "clk" TNM_NET = "clk"; TIMESPEC "TS_clk" = PERIOD "clk" 2.5 ns HIGH 50 %;

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library ieee; use ieee.std_logic_1164.all; entity data_control is port ( clk : in std_logic; reset : in std_logic; rd_data_cha : in st

#Build: Synplify Pro 8.8, Build 008R, Dec 7 2006 #install: Y:\XILI\Synplify_8_8\fpga_88 #OS: Windows 2000 5.0 #Hostname: SJC-XILISTG1 #Implementation: vhdl #Fri Mar 16 10:05:14 2007 $ Sta

NET "clk" TNM_NET = "clk"; TIMESPEC "TS_clk" = PERIOD "clk" 2.5 ns HIGH 50 %;

module data_control (input clk, input reset, input [3:0] pn_lock_rd_clk, input [7:0] rd_data_cha, input [7:0] rd_data_chb, input [7:0] rd_data_chc,

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