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Remote Control 的代码
control.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use work.mydefine.all;
entity control is
port(c_en:in std_logic;
input:in std_logic_vector(7 downto 0);
clk:in std_
control.vhd
--
-- Definition of a dual port ROM for KCPSM2 or KCPSM3 program defined by control.psm
-- and assmbled using KCPSM2 or KCPSM3 assembler.
--
-- This file has been modified for use with the Designi
control.vhd
--
-- Definition of a dual port ROM for KCPSM2 or KCPSM3 program defined by control.psm
-- and assmbled using KCPSM2 or KCPSM3 assembler.
--
-- This file has been modified for use with the Designi
control.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use work.mydefine.all;
entity control is
port(c_en:in std_logic;
input:in std_logic_vector(7 downto 0);
clk:in std_
control.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use work.mydefine.all;
entity control is
port(c_en:in std_logic;
input:in std_logic_vector(7 downto 0);
clk:in std_
control.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use work.mydefine.all;
entity control is
port(c_en:in std_logic;
input:in std_logic_vector(7 downto 0);
clk:in std_
control.edf
(edif control
(edifVersion 2 0 0)
(edifLevel 0)
(keywordMap (keywordLevel 0))
(status
(written
(timeStamp 2007 11 23 13 41 36)
(author "Synplicity, Inc.")
(progra
control.tcl
project add_assignment "" "control" "" "" "EDA_DESIGN_ENTRY_SYNTHESIS_TOOL" "SYNPLIFY"
project add_assignment "" "eda_design_synthesis" "" "" EDA_INPUT_DATA_FORMAT EDIF
project add_assignment "" "ed
control.tlg
Synthesizing work.control.body_control
Post processing for work.control.body_control
@W:"H:\can\cpld\rev_1\control.vhd":367:4:367:5|Optimizing register bit wr_a_up(0) to a constant 0
@W:"H:\can\cpl
control.sat
define_design_name {control}
define_synthesis -family MAX7000
define_clock {|sysclk} -period 1000.000
define_clock {|iow} -period 1000.000
define_clock {|ior} -period 1000.000
define_clock {|wrb}