代码搜索结果

Extra Info: Performing register packing on registers with non-logic cell location assignments Extra Info: Completed register packing on registers with non-logic cell location assignments Extra Info:

Fitter Status : Successful - Wed Oct 10 21:54:49 2007 Quartus II Version : 6.0 Build 178 04/27/2006 SJ Full Version Revision Name : control Top-level Entity Name : control Family : Stratix Device

Timing Analyzer report for control Wed Oct 10 21:54:59 2007 Version 6.0 Build 178 04/27/2006 SJ Full Version --------------------- ; Table of Contents ; --------------------- 1. Legal Noti

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity control_display is Port (clk : in std_logic; -- 1khz; start :

/* WARNING: Do NOT edit the input and output ports in this file in a text editor if you plan to continue editing the block that represents it in the Block Editor! File corruption is VERY likely to

/* WARNING: Do NOT edit the input and output ports in this file in a text editor if you plan to continue editing the block that represents it in the Block Editor! File corruption is VERY likely to

/* WARNING: Do NOT edit the input and output ports in this file in a text editor if you plan to continue editing the block that represents it in the Block Editor! File corruption is VERY likely to

Fitter report for control Sun Feb 25 04:49:57 2007 Version 6.0 Build 178 04/27/2006 SJ Full Version --------------------- ; Table of Contents ; --------------------- 1. Legal Notice 2.

# Copyright (C) 1991-2006 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any outpu