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library IEEE; use IEEE.std_logic_1164.all; use work.cpu_lib.all; entity control1 is port( clock : in std_logic; reset : in std_logic; instrReg : in bit16; compout : in std_logic; ready : i

Version 5.0 Build 168 06/22/2005 Service Pack 1.21 SJ Full Version 32 1637 OFF OFF OFF OFF OFF FV_OFF VRSM_ON VHSM_ON 0 # entity control1 # logic_option { AUTO_RAM_RECOGNITION ON } #

# Copyright (C) 1991-2005 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any

-- Copyright (C) 1991-2005 Altera Corporation -- Your use of Altera Corporation's design tools, logic functions -- and other software and tools, and its AMPP partner logic -- functions,

[ProjectWorkspace] ptn_Child1=Frames ptn_Child2=ActionPoints [ProjectWorkspace.Frames] ptn_Child1=ChildFrames [ProjectWorkspace.Frames.ChildFrames] ptn_Child1=Document-0 ptn_Child2=Document-1

module control_interface( CLK, RESET_N, CMD, ADDR, REF_ACK, INIT_ACK, CM_ACK, NOP, READA, WRITEA, REFRESH,