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C51 COMPILER V8.02 MAIN 01/14/2009 21:15:27 PAGE 1 C51 COMPILER V8.02, COMPILATION OF MODULE MAIN OBJECT MODULE PLACED IN ma

#include #include "initial.h" #define sysclk 22118400 // SYSCLK frequency in Hz xdata long uint value,value1; xdata long uint i=0; uchar t,stop0; uint AD_nu

# Copyright (C) 1991-2006 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any outpu

ena conf t host fr int s0 encap fram exit fram sw int s0 fram intf dce no fram inver fram route 11 int s2 111 clock rate 56000 no shut int s2 encap fram no fram inver clock rate 56000

/****************************************************************************/ /* */ /* Copyright (c) 2005, 老树

/****************************************************************************/ /* */ /* Copyright (c) 2005, 老树

#include #include #include #include "numkeyp.h" #include "keydef.h" #include "cursor.h" #include "g_func.h" #include "global.h" #include "powerkey.h" #includ

#include "common.h" //设置DAC电压 //channel=1:A通道 //channel=2:B通道 //value:0-4095 //输出电压=2.5*2*value/4096 //注意:因为VCC=5V,故输出接近5V的电压可能会有因供电电压限制产生的误差 void Set_DAC(unsigned char channel,unsigned int

/************************************************************************************************/ /* hardware connection */ /****************************

% Direct link if (use_direct_link == 1) [channel(1), rx] = add_channel_effect(channel(1), rx,... signal.symbol_sequence); rx = rx_correct_phaseshift(rx, channel(1).attenuation.phi); end % ------