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.i 3 .o 6 .s 6 .p 17 .reset Rst .resettype async .clock Clk .resetstate st1 .type fdr .ilb In0 In1 In2 .ob Out0 Out1 Out2 Out3 Out4 Out5 .obdefault 000000 .ffname state .fftype d .usedc

--altsyncram ADDRESS_ACLR_A="NONE" ADDRESS_ACLR_B="NONE" ADDRESS_REG_B="CLOCK1" BYTE_SIZE=8 CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CLOCK_ENABLE_INPUT_A="NORMAL" CLOCK_ENABLE_OUTPUT_A="NORMAL" CYCLONEII

--altsyncram ADDRESS_ACLR_A="NONE" ADDRESS_ACLR_B="NONE" ADDRESS_REG_B="CLOCK1" BYTE_SIZE=8 CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CLOCK_ENABLE_INPUT_A="NORMAL" CLOCK_ENABLE_OUTPUT_A="NORMAL" CYCLONEII

.i 3 .o 6 .s 6 .p 17 .reset Rst .resettype async .clock Clk .resetstate st1 .type fdr .ilb In0 In1 In2 .ob Out0 Out1 Out2 Out3 Out4 Out5 .obdefault 000000 .ffname state .fftype d .usedc

.i 3 .o 6 .s 6 .p 17 .reset Rst .resettype async .clock Clk .resetstate st1 .type fdr .ilb In0 In1 In2 .ob Out0 Out1 Out2 Out3 Out4 Out5 .obdefault 000000 .ffname state .fftype d .usedc

.i 3 .o 6 .s 6 .p 17 .reset Rst .resettype async .clock Clk .resetstate st1 .type fdr .ilb In0 In1 In2 .ob Out0 Out1 Out2 Out3 Out4 Out5 .obdefault 000000 .ffname state .fftype d .usedc

.i 3 .o 6 .s 6 .p 17 .reset Rst .resettype async .clock Clk .resetstate st1 .type fdr .ilb In0 In1 In2 .ob Out0 Out1 Out2 Out3 Out4 Out5 .obdefault 000000 .ffname state .fftype d .usedc

.i 3 .o 6 .s 6 .p 17 .reset Rst .resettype async .clock Clk .resetstate st1 .type fdr .ilb In0 In1 In2 .ob Out0 Out1 Out2 Out3 Out4 Out5 .obdefault 000000 .ffname state .fftype d .usedc

.i 3 .o 6 .s 6 .p 17 .reset Rst .resettype async .clock Clk .resetstate st1 .type fdr .ilb In0 In1 In2 .ob Out0 Out1 Out2 Out3 Out4 Out5 .obdefault 000000 .ffname state .fftype d .usedc

.i 3 .o 6 .s 6 .p 17 .reset Rst .resettype async .clock Clk .resetstate st1 .type fdr .ilb In0 In1 In2 .ob Out0 Out1 Out2 Out3 Out4 Out5 .obdefault 000000 .ffname state .fftype d .usedc