代码搜索：RS编码
找到约 10,000 项符合「RS编码」的源代码
代码结果 10,000
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drc fpga_40rs232.drc
WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net CLK1 is sourced by a
combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip
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prj fpga_40rs232.prj
verilog work serial.v
verilog work diag.v
verilog work fpga_40XRS232.v
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par fpga_40rs232.par
Release 6.2i Par G.28
Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.
TOMWANG:: Sun Feb 26 16:53:28 2006
C:/Xilinx/bin/nt/par.exe -w -intstyle ise -ol std -t 1 fpga_40RS232_map.ncd
fpg
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pcf fpga_40rs232.pcf
SCHEMATIC START ;
// created by map version G.28 on Sun Feb 26 16:53:27 2006
COMP "reset1" LOCATE = SITE "P163" LEVEL 1;
COMP "CTS" LOCATE = SITE "P127" LEVEL 1;
COMP "RD" LOCATE = SITE "P13
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gfl rs23240x_flowplus.gfl
# XST flow : Creating project file
fpga_40RS232.prj
# xst flow : RunXST
fpga_40RS232.prj
__projnav/fpga_40RS232.xst
./xst
# XST flow : Creating project file
fpga_40RS232.prj
# xst flow : RunXS
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xst fpga_40rs232.xst
set -tmpdir __projnav
set -xsthdpdir ./xst
run
-ifn fpga_40RS232.prj
-ifmt mixed
-ofn fpga_40RS232
-ofmt NGC
-p xc2s200-5-pq208
-top fpga_40RS232
-opt_mode Speed
-opt_level 1
-iuc NO
-lso
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syr fpga_40rs232.syr
Release 6.2i - xst G.28
Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.
--> Parameter TMPDIR set to __projnav
CPU : 0.00 / 0.53 s | Elapsed : 0.00 / 0.00 s
--> Parameter xsthdpdir set to
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bld fpga_40rs232.bld
Release 6.2i - ngdbuild G.28
Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.
Command Line: ngdbuild -intstyle ise -dd
f:\trainsilicon\fpgaschool\testcade\fpga40xc200\basic2\rs232\ise\rs23