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www.eeworm.com/read/351211/10673494
vhd ram.vhd
-- Behavioral description of dual-port SRAM with :
-- Active High write enable (WE)
-- Active High read enable (RE)
-- Rising clock edge (Clock)
library ieee;
use ieee.std_logic_1164.all;
use IE
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vhd ram.vhd
-- Behavioral description of dual-port SRAM with :
-- Active High write enable (WE)
-- Active High read enable (RE)
-- Rising clock edge (Clock)
library ieee;
use ieee.std_logic_1164.all;
use IE
www.eeworm.com/read/421425/10736988
vhd ram.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.Numeric_Std.all;
entity sync_ram1 is
port (
clock : in std_logic;
we,rd : in std_logic;
address : in std_logic_vector(0 to 9);
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ini ram.ini
/***********************************************************************/
/* This file is part of the ARM Compiler package */
/* Copyright KEIL ELEKTRONIK GmbH 1992-2004
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v ram.v
// megafunction wizard: %RAM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: ram.v
// Me
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v ram.v
//////////////////////////////////////////////////////////////////////
//// ////
//// 8051 data ram
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ram_vector
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obj ram.obj
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c ram.c
#include
// Function Prototypes with attribute definitions
void IRQ_Handler() __irq;
/********************************************************************/
/*
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lst ram.lst
ARM COMPILER V2.42, RAM 09/01/06 14:42:49 PAGE 1
ARM COMPILER V2.42, COMPILATION OF MODULE RAM
OBJECT MODULE PLACED IN RA