代码搜索：RAM配置
找到约 10,000 项符合「RAM配置」的源代码
代码结果 10,000
www.eeworm.com/read/236764/14000051
v vga_osd_ram.v
module VGA_OSD_RAM ( // Read Out Side
oRed,
oGreen,
oBlue,
iVGA_ADDR,
iVGA_CLK,
// Write In Side
iWR_DATA,
iWR_ADDR,
iWR_EN,
iWR_C
www.eeworm.com/read/235944/14039718
mac sam7_ram.mac
// File: SAM7_RAM.mac
//
// ---------------------------------------------------------
__var i;
__var pt;
execUserPreload() {
PllSetting();
//* 为Flash 0地址区的代码设置 RAM 存储器地址0x00200000
www.eeworm.com/read/235932/14040710
mac sam7_ram.mac
// File: SAM7_RAM.mac
//
// ---------------------------------------------------------
__var i;
__var pt;
execUserPreload() {
PllSetting();
//* 为Flash 0地址区的代码设置 RAM 存储器地址0x00200000
www.eeworm.com/read/235929/14041136
mac sam7_ram.mac
// File: SAM7_RAM.mac
//
// ---------------------------------------------------------
__var i;
__var pt;
execUserPreload() {
PllSetting();
//* 为Flash 0地址区的代码设置 RAM 存储器地址0x00200000
www.eeworm.com/read/132793/14072679
v map_lpm_ram.v
module map_lpm_ram(dataout,datain,addr,we,inclk,outclk);
input[15:0] datain;
input[7:0] addr;
input we,inclk,outclk;
output[15:0] dataout;
lpm_ram_dq ram(.data(datain),.address(addr),.we(we),.i
www.eeworm.com/read/235392/14072771
v or1200_ic_ram.v
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's IC RAMs
www.eeworm.com/read/235392/14072826
v or1200_dc_ram.v
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's DC RAMs
www.eeworm.com/read/235125/14085069
h daytona_ram_variables.h
;/* hardware variables for Daytona */
;/* v0.1 Ador Reodique 4/20/00
;/* Modified by Jeff Burgess for 8x oversampling */
; variables for Daytona Serial and SAR routines
T2 ds
www.eeworm.com/read/235012/14088792
v dp_async_ram.v
//////////////////////////////////////////////////////////////////////
//// ////
//// File name "dp_async_ram.v"
www.eeworm.com/read/203569/15355543
v map_lpm_ram.v
module map_lpm_ram(dataout,datain,addr,we,inclk,outclk);
input[15:0] datain;
input[7:0] addr;
input we,inclk,outclk;
output[15:0] dataout;
lpm_ram_dq ram(.data(datain),.address(addr),.we(we),.i